X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Favr%2Fdrv%2Fser_avr.c;h=2d25fbeb27dd1176736f9a8a47d2eb23aac3f72a;hb=0f60d6b24cf8ec1c9bd8dca82fed6325932c5aca;hp=f4cf42de0d76f526711e333553f1402c96d087fe;hpb=e603425ebb795a273a11c073033544f6a51b9247;p=bertos.git

diff --git a/bertos/cpu/avr/drv/ser_avr.c b/bertos/cpu/avr/drv/ser_avr.c
index f4cf42de..2d25fbeb 100644
--- a/bertos/cpu/avr/drv/ser_avr.c
+++ b/bertos/cpu/avr/drv/ser_avr.c
@@ -26,17 +26,16 @@
  * invalidate any other reasons why the executable file might be covered by
  * the GNU General Public License.
  *
- * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
+ * Copyright 2003, 2004, 2010 Develer S.r.l. (http://www.develer.com/)
  * Copyright 2000 Bernie Innocenti <bernie@codewiz.org>
  *
  * -->
  *
  * \brief AVR UART and SPI I/O driver (Implementation)
  *
- * \version $Id$
- *
  * \author Bernie Innocenti <bernie@codewiz.org>
  * \author Stefano Fedrigo <aleph@develer.com>
+ * \author Luca Ottaviano <lottaviano@develer.com>
  */
 
 #include "hw/hw_ser.h"  /* Required for bus macros overrides */
@@ -46,6 +45,7 @@
 
 #include <cfg/macros.h> /* DIV_ROUND */
 #include <cfg/debug.h>
+#include <cfg/cfg_arch.h> // ARCH_NIGHTTEST
 
 #include <drv/ser.h>
 #include <drv/ser_p.h>
@@ -84,6 +84,16 @@
 	#define BIT_RXEN1  RXEN1
 	#define BIT_TXEN1  TXEN1
 	#define BIT_UDRIE1 UDRIE1
+#elif CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P
+	#define BIT_RXCIE0 RXCIE0
+	#define BIT_RXEN0  RXEN0
+	#define BIT_TXEN0  TXEN0
+	#define BIT_UDRIE0 UDRIE0
+
+	#define BIT_RXCIE1 RXCIE0
+	#define BIT_RXEN1  RXEN0
+	#define BIT_TXEN1  TXEN0
+	#define BIT_UDRIE1 UDRIE0
 #else
 	#define BIT_RXCIE0 RXCIE
 	#define BIT_RXEN0  RXEN
@@ -247,7 +257,16 @@
 	#define SPI_SCK_BIT   PB1
 	#define SPI_MOSI_BIT  PB2
 	#define SPI_MISO_BIT  PB3
-#elif CPU_AVR_ATMEGA8
+// TODO: these bits are the same as ATMEGA8 but the defines in avr-gcc are different.
+// They should be the same!
+#elif CPU_AVR_ATMEGA328P
+	#define SPI_PORT      PORTB
+	#define SPI_DDR       DDRB
+	#define SPI_SS_BIT    PORTB2
+	#define SPI_SCK_BIT   PORTB5
+	#define SPI_MOSI_BIT  PORTB3
+	#define SPI_MISO_BIT  PORTB4
+#elif CPU_AVR_ATMEGA8 || CPU_AVR_ATMEGA168
 	#define SPI_PORT      PORTB
 	#define SPI_DDR       DDRB
 	#define SPI_SS_BIT    PB2
@@ -261,6 +280,11 @@
 /* USART register definitions */
 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA1281
 	#define AVR_HAS_UART1 1
+#elif CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P
+	#define AVR_HAS_UART1 0
+	#define USART0_UDRE_vect USART_UDRE_vect
+	#define USART0_RX_vect USART_RX_vect
+	#define USART0_TX_vect USART_TX_vect
 #elif CPU_AVR_ATMEGA8
 	#define AVR_HAS_UART1 0
 	#define UCSR0A UCSRA
@@ -269,18 +293,18 @@
 	#define UDR0   UDR
 	#define UBRR0L UBRRL
 	#define UBRR0H UBRRH
-	#define SIG_UART0_DATA SIG_UART_DATA
-	#define SIG_UART0_RECV SIG_UART_RECV
-	#define SIG_UART0_TRANS SIG_UART_TRANS
+	#define USART0_UDRE_vect USART_UDRE_vect
+	#define USART0_RX_vect USART_RX_vect
+	#define USART0_TX_vect USART_TX_vect
 #elif CPU_AVR_ATMEGA103
 	#define AVR_HAS_UART1 0
 	#define UCSR0B UCR
 	#define UDR0   UDR
 	#define UCSR0A USR
 	#define UBRR0L UBRR
-	#define SIG_UART0_DATA SIG_UART_DATA
-	#define SIG_UART0_RECV SIG_UART_RECV
-	#define SIG_UART0_TRANS SIG_UART_TRANS
+	#define USART0_UDRE_vect USART_UDRE_vect
+	#define USART0_RX_vect USART_RX_vect
+	#define USART0_TX_vect USART_TX_vect
 #else
 	#error Unknown architecture
 #endif
@@ -453,7 +477,7 @@ static void spi_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct
 	 * - as input but tied high forever!
 	 * This driver set the pin as output.
 	 */
-	#warning SPI SS pin set as output for proper operation, check schematics for possible conflicts.
+	#warning FIXME:SPI SS pin set as output for proper operation, check schematics for possible conflicts.
 	ATOMIC(SPI_DDR |= BV(SPI_SS_BIT));
 
 	ATOMIC(SPI_DDR &= ~BV(SPI_MISO_BIT));
@@ -644,7 +668,7 @@ struct SerialHardware *ser_hw_getdesc(int unit)
 #if CONFIG_SER_HWHANDSHAKE
 
 /// This interrupt is triggered when the CTS line goes high
-SIGNAL(SIG_CTS)
+DECLARE_ISR(SIG_CTS)
 {
 	// Re-enable UDR empty interrupt and TX, then disable CTS interrupt
 	UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0);
@@ -657,7 +681,7 @@ SIGNAL(SIG_CTS)
 /**
  * Serial 0 TX interrupt handler
  */
-SIGNAL(USART0_UDRE_vect)
+DECLARE_ISR(USART0_UDRE_vect)
 {
 	SER_STROBE_ON;
 
@@ -705,7 +729,7 @@ SIGNAL(USART0_UDRE_vect)
  * otherwise we'd stop the serial port with some data
  * still pending in the buffer.
  */
-SIGNAL(SIG_UART0_TRANS)
+DECLARE_ISR(USART0_TX_vect)
 {
 	SER_STROBE_ON;
 
@@ -728,7 +752,7 @@ SIGNAL(SIG_UART0_TRANS)
 /**
  * Serial 1 TX interrupt handler
  */
-SIGNAL(USART1_UDRE_vect)
+DECLARE_ISR(USART1_UDRE_vect)
 {
 	SER_STROBE_ON;
 
@@ -766,7 +790,7 @@ SIGNAL(USART1_UDRE_vect)
  *
  * \sa port 0 TX complete handler.
  */
-SIGNAL(USART1_TX_vect)
+DECLARE_ISR(USART1_TX_vect)
 {
 	SER_STROBE_ON;
 
@@ -801,7 +825,7 @@ SIGNAL(USART1_TX_vect)
  *       RXCIE is cleared.  Unfortunately the RXC flag is read-only
  *       and can't be cleared by code.
  */
-SIGNAL(USART0_RX_vect)
+DECLARE_ISR(USART0_RX_vect)
 {
 	SER_STROBE_ON;
 
@@ -849,9 +873,9 @@ SIGNAL(USART0_RX_vect)
  * is heavily loaded, because an interrupt could be retriggered
  * when executing the handler prologue before RXCIE is disabled.
  *
- * \see SIGNAL(USART1_RX_vect)
+ * \see DECLARE_ISR(USART1_RX_vect)
  */
-SIGNAL(USART1_RX_vect)
+DECLARE_ISR(USART1_RX_vect)
 {
 	SER_STROBE_ON;
 
@@ -892,7 +916,7 @@ SIGNAL(USART1_RX_vect)
 /**
  * SPI interrupt handler
  */
-SIGNAL(SIG_SPI)
+DECLARE_ISR(SPI_STC_vect)
 {
 	SER_STROBE_ON;