X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Favr%2Fdrv%2Fser_avr.c;h=a4328f41b8552b60af93b6919b098484969672d3;hb=0e8d3b095f4b5ba3ac5c080c0e9edb5226c38bad;hp=11a6c65c024c7d628f5041056d556d238eeab21e;hpb=6be047844350e6988c1a82a68ff8572fb2b60b57;p=bertos.git

diff --git a/bertos/cpu/avr/drv/ser_avr.c b/bertos/cpu/avr/drv/ser_avr.c
index 11a6c65c..a4328f41 100644
--- a/bertos/cpu/avr/drv/ser_avr.c
+++ b/bertos/cpu/avr/drv/ser_avr.c
@@ -355,6 +355,13 @@
 	#define SPI_SCK_BIT   PB5
 	#define SPI_MOSI_BIT  PB3
 	#define SPI_MISO_BIT  PB4
+#elif CPU_AVR_ATMEGA32
+	#define SPI_PORT      PORTB
+	#define SPI_DDR       DDRB
+	#define SPI_SS_BIT    PB4
+	#define SPI_SCK_BIT   PB7
+	#define SPI_MOSI_BIT  PB5
+	#define SPI_MISO_BIT  PB6
 #else
 	#error Unknown architecture
 #endif
@@ -375,7 +382,7 @@
 	#define USART0_UDRE_vect USART_UDRE_vect
 	#define USART0_RX_vect USART_RX_vect
 	#define USART0_TX_vect USART_TX_vect
-#elif CPU_AVR_ATMEGA8
+#elif CPU_AVR_ATMEGA8 || CPU_AVR_ATMEGA32
 	#define AVR_HAS_UART1 0
 	#define AVR_HAS_UART2 0
 	#define AVR_HAS_UART3 0
@@ -385,9 +392,11 @@
 	#define UDR0   UDR
 	#define UBRR0L UBRRL
 	#define UBRR0H UBRRH
+	#define UPM01  UPM1
+	#define UPM00  UPM0
 	#define USART0_UDRE_vect USART_UDRE_vect
-	#define USART0_RX_vect USART_RX_vect
-	#define USART0_TX_vect USART_TX_vect
+	#define USART0_RX_vect USART_RXC_vect
+	#define USART0_TX_vect USART_TXC_vect
 #elif CPU_AVR_ATMEGA103
 	#define AVR_HAS_UART1 0
 	#define AVR_HAS_UART2 0
@@ -1080,22 +1089,6 @@ DECLARE_ISR(USART2_UDRE_vect)
 		UARTDescs[SER_UART2].sending = false;
 #endif
 	}
-
-/**
- * ATMEGA64, 128 and 103 do not have more than 2 USARTs
-
-#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
-	else if (!IS_CTS_ON)
-	{
-		// Disable rx interrupt and tx, enable CTS interrupt
-		// UNTESTED
-		UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1);
-		EIFR |= EIMSKF_CTS;
-		EIMSK |= EIMSKF_CTS;
-	}
-#endif
-
- */
 	else
 	{
 		char c = fifo_pop(txfifo);
@@ -1148,22 +1141,6 @@ DECLARE_ISR(USART3_UDRE_vect)
 		UARTDescs[SER_UART3].sending = false;
 #endif
 	}
-
-/**
- * ATMEGA64, 128 and 103 do not have more than 2 USARTs
-
-#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
-	else if (!IS_CTS_ON)
-	{
-		// Disable rx interrupt and tx, enable CTS interrupt
-		// UNTESTED
-		UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1);
-		EIFR |= EIMSKF_CTS;
-		EIMSK |= EIMSKF_CTS;
-	}
-#endif
-
- */
 	else
 	{
 		char c = fifo_pop(txfifo);