X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Favr%2Fdrv%2Fser_avr.c;h=d3cc743d0d6ca0e32d7d492832bccfd301a509b5;hb=2c5f3d04467211d59b9387abe73c1f286ea74806;hp=955ab8ebc0c52bc7fee8057ddad5de9e2fb341c8;hpb=6eb6ebb5ae5953a27977f0ef66a36344462b949a;p=bertos.git

diff --git a/bertos/cpu/avr/drv/ser_avr.c b/bertos/cpu/avr/drv/ser_avr.c
index 955ab8eb..d3cc743d 100644
--- a/bertos/cpu/avr/drv/ser_avr.c
+++ b/bertos/cpu/avr/drv/ser_avr.c
@@ -40,7 +40,7 @@
  */
 
 #include "hw/hw_ser.h"  /* Required for bus macros overrides */
-#include "hw/hw_cpu.h"  /* CLOCK_FREQ */
+#include <hw/hw_cpufreq.h>  /* CPU_FREQ */
 
 #include "cfg/cfg_ser.h"
 
@@ -377,7 +377,7 @@ static void uart0_enabletxirq(struct SerialHardware *_hw)
 static void uart0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
 {
 	/* Compute baud-rate period */
-	uint16_t period = DIV_ROUND(CLOCK_FREQ / 16UL, rate) - 1;
+	uint16_t period = DIV_ROUND(CPU_FREQ / 16UL, rate) - 1;
 
 #if !CPU_AVR_ATMEGA103
 	UBRR0H = (period) >> 8;
@@ -430,7 +430,7 @@ static void uart1_enabletxirq(struct SerialHardware *_hw)
 static void uart1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
 {
 	/* Compute baud-rate period */
-	uint16_t period = DIV_ROUND(CLOCK_FREQ / 16UL, rate) - 1;
+	uint16_t period = DIV_ROUND(CPU_FREQ / 16UL, rate) - 1;
 
 	UBRR1H = (period) >> 8;
 	UBRR1L = (period);
@@ -533,7 +533,7 @@ static void spi_starttx(struct SerialHardware *_hw)
 {
 	struct AvrSerial *hw = (struct AvrSerial *)_hw;
 
-	cpuflags_t flags;
+	cpu_flags_t flags;
 	IRQ_SAVE_DISABLE(flags);
 
 	/* Send data only if the SPI is not already transmitting */
@@ -664,7 +664,7 @@ struct SerialHardware *ser_hw_getdesc(int unit)
 SIGNAL(SIG_CTS)
 {
 	// Re-enable UDR empty interrupt and TX, then disable CTS interrupt
-	UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
+	UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0);
 	EIMSK &= ~EIMSKF_CTS;
 }
 
@@ -692,7 +692,7 @@ SIGNAL(USART0_UDRE_vect)
 	{
 		// Disable rx interrupt and tx, enable CTS interrupt
 		// UNTESTED
-		UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
+		UCSR0B = BV(BIT_RXCIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0);
 		EIFR |= EIMSKF_CTS;
 		EIMSK |= EIMSKF_CTS;
 	}
@@ -733,7 +733,7 @@ SIGNAL(SIG_UART0_TRANS)
 		UARTDescs[SER_UART0].sending = false;
 	}
 	else
-		UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
+		UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0);
 
 	SER_STROBE_OFF;
 }
@@ -763,7 +763,7 @@ SIGNAL(USART1_UDRE_vect)
 	{
 		// Disable rx interrupt and tx, enable CTS interrupt
 		// UNTESTED
-		UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
+		UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1);
 		EIFR |= EIMSKF_CTS;
 		EIMSK |= EIMSKF_CTS;
 	}
@@ -783,7 +783,7 @@ SIGNAL(USART1_UDRE_vect)
  *
  * \sa port 0 TX complete handler.
  */
-SIGNAL(SIG_UART1_TRANS)
+SIGNAL(USART1_TX_vect)
 {
 	SER_STROBE_ON;
 
@@ -794,7 +794,7 @@ SIGNAL(SIG_UART1_TRANS)
 		UARTDescs[SER_UART1].sending = false;
 	}
 	else
-		UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
+		UCSR1B = BV(BIT_RXCIE1) | BV(BIT_UDRIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1);
 
 	SER_STROBE_OFF;
 }