X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Favr%2Fdrv%2Fser_avr.c;h=d6de8243dbb27056be9a71158b2d97090bd97da2;hb=32d1445272120a254d77ce8d1af1f527da7a2c17;hp=d49da30a76d9d200c127a25f3a88c567a764c68f;hpb=df94a4b7d8102b20810f889fbc926ac4823b61d9;p=bertos.git diff --git a/bertos/cpu/avr/drv/ser_avr.c b/bertos/cpu/avr/drv/ser_avr.c index d49da30a..d6de8243 100644 --- a/bertos/cpu/avr/drv/ser_avr.c +++ b/bertos/cpu/avr/drv/ser_avr.c @@ -40,18 +40,19 @@ */ #include "hw/hw_ser.h" /* Required for bus macros overrides */ -#include "hw/hw_cpu.h" /* CLOCK_FREQ */ +#include /* CPU_FREQ */ #include "cfg/cfg_ser.h" #include /* DIV_ROUND */ #include +#include // ARCH_NIGHTTEST #include #include #include -#include +#include #include @@ -286,23 +287,6 @@ #endif -/** - * \def CONFIG_SER_STROBE - * - * This is a debug facility that can be used to - * monitor SER interrupt activity on an external pin. - * - * To use strobes, redefine the macros SER_STROBE_ON, - * SER_STROBE_OFF and SER_STROBE_INIT and set - * CONFIG_SER_STROBE to 1. - */ -#if !defined(CONFIG_SER_STROBE) || !CONFIG_SER_STROBE - #define SER_STROBE_ON do {/*nop*/} while(0) - #define SER_STROBE_OFF do {/*nop*/} while(0) - #define SER_STROBE_INIT do {/*nop*/} while(0) -#endif - - /* From the high-level serial driver */ extern struct Serial *ser_handles[SER_CNT]; @@ -377,7 +361,7 @@ static void uart0_enabletxirq(struct SerialHardware *_hw) static void uart0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate) { /* Compute baud-rate period */ - uint16_t period = DIV_ROUND(CLOCK_FREQ / 16UL, rate) - 1; + uint16_t period = DIV_ROUND(CPU_FREQ / 16UL, rate) - 1; #if !CPU_AVR_ATMEGA103 UBRR0H = (period) >> 8; @@ -430,7 +414,7 @@ static void uart1_enabletxirq(struct SerialHardware *_hw) static void uart1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate) { /* Compute baud-rate period */ - uint16_t period = DIV_ROUND(CLOCK_FREQ / 16UL, rate) - 1; + uint16_t period = DIV_ROUND(CPU_FREQ / 16UL, rate) - 1; UBRR1H = (period) >> 8; UBRR1L = (period); @@ -470,7 +454,7 @@ static void spi_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct * - as input but tied high forever! * This driver set the pin as output. */ - #warning SPI SS pin set as output for proper operation, check schematics for possible conflicts. + #warning FIXME:SPI SS pin set as output for proper operation, check schematics for possible conflicts. ATOMIC(SPI_DDR |= BV(SPI_SS_BIT)); ATOMIC(SPI_DDR &= ~BV(SPI_MISO_BIT)); @@ -533,7 +517,7 @@ static void spi_starttx(struct SerialHardware *_hw) { struct AvrSerial *hw = (struct AvrSerial *)_hw; - cpuflags_t flags; + cpu_flags_t flags; IRQ_SAVE_DISABLE(flags); /* Send data only if the SPI is not already transmitting */ @@ -661,10 +645,10 @@ struct SerialHardware *ser_hw_getdesc(int unit) #if CONFIG_SER_HWHANDSHAKE /// This interrupt is triggered when the CTS line goes high -SIGNAL(SIG_CTS) +DECLARE_ISR(SIG_CTS) { // Re-enable UDR empty interrupt and TX, then disable CTS interrupt - UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); + UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); EIMSK &= ~EIMSKF_CTS; } @@ -674,7 +658,7 @@ SIGNAL(SIG_CTS) /** * Serial 0 TX interrupt handler */ -SIGNAL(USART0_UDRE_vect) +DECLARE_ISR(USART0_UDRE_vect) { SER_STROBE_ON; @@ -692,7 +676,7 @@ SIGNAL(USART0_UDRE_vect) { // Disable rx interrupt and tx, enable CTS interrupt // UNTESTED - UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); + UCSR0B = BV(BIT_RXCIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); EIFR |= EIMSKF_CTS; EIMSK |= EIMSKF_CTS; } @@ -722,7 +706,7 @@ SIGNAL(USART0_UDRE_vect) * otherwise we'd stop the serial port with some data * still pending in the buffer. */ -SIGNAL(SIG_UART0_TRANS) +DECLARE_ISR(SIG_UART0_TRANS) { SER_STROBE_ON; @@ -733,7 +717,7 @@ SIGNAL(SIG_UART0_TRANS) UARTDescs[SER_UART0].sending = false; } else - UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); + UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); SER_STROBE_OFF; } @@ -745,7 +729,7 @@ SIGNAL(SIG_UART0_TRANS) /** * Serial 1 TX interrupt handler */ -SIGNAL(USART1_UDRE_vect) +DECLARE_ISR(USART1_UDRE_vect) { SER_STROBE_ON; @@ -763,7 +747,7 @@ SIGNAL(USART1_UDRE_vect) { // Disable rx interrupt and tx, enable CTS interrupt // UNTESTED - UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); + UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); EIFR |= EIMSKF_CTS; EIMSK |= EIMSKF_CTS; } @@ -783,7 +767,7 @@ SIGNAL(USART1_UDRE_vect) * * \sa port 0 TX complete handler. */ -SIGNAL(SIG_UART1_TRANS) +DECLARE_ISR(USART1_TX_vect) { SER_STROBE_ON; @@ -794,7 +778,7 @@ SIGNAL(SIG_UART1_TRANS) UARTDescs[SER_UART1].sending = false; } else - UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); + UCSR1B = BV(BIT_RXCIE1) | BV(BIT_UDRIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); SER_STROBE_OFF; } @@ -818,7 +802,7 @@ SIGNAL(SIG_UART1_TRANS) * RXCIE is cleared. Unfortunately the RXC flag is read-only * and can't be cleared by code. */ -SIGNAL(USART0_RX_vect) +DECLARE_ISR(USART0_RX_vect) { SER_STROBE_ON; @@ -866,9 +850,9 @@ SIGNAL(USART0_RX_vect) * is heavily loaded, because an interrupt could be retriggered * when executing the handler prologue before RXCIE is disabled. * - * \see SIGNAL(USART1_RX_vect) + * \see DECLARE_ISR(USART1_RX_vect) */ -SIGNAL(USART1_RX_vect) +DECLARE_ISR(USART1_RX_vect) { SER_STROBE_ON; @@ -909,7 +893,7 @@ SIGNAL(USART1_RX_vect) /** * SPI interrupt handler */ -SIGNAL(SIG_SPI) +DECLARE_ISR(SIG_SPI) { SER_STROBE_ON;