X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Favr%2Fdrv%2Fser_avr.c;h=d6de8243dbb27056be9a71158b2d97090bd97da2;hb=4daefac32ad5a2198f911584f1e5abea001d6062;hp=c4d4994520929b070c1c777ae2ed9fcdf3fccf98;hpb=4cc44c9888a0336b9d01121ec0b7ad95f4a76195;p=bertos.git diff --git a/bertos/cpu/avr/drv/ser_avr.c b/bertos/cpu/avr/drv/ser_avr.c index c4d49945..d6de8243 100644 --- a/bertos/cpu/avr/drv/ser_avr.c +++ b/bertos/cpu/avr/drv/ser_avr.c @@ -40,18 +40,19 @@ */ #include "hw/hw_ser.h" /* Required for bus macros overrides */ -#include "hw/hw_cpu.h" /* CLOCK_FREQ */ +#include /* CPU_FREQ */ #include "cfg/cfg_ser.h" #include /* DIV_ROUND */ #include +#include // ARCH_NIGHTTEST #include #include #include -#include +#include #include @@ -286,25 +287,8 @@ #endif -/** - * \def CONFIG_SER_STROBE - * - * This is a debug facility that can be used to - * monitor SER interrupt activity on an external pin. - * - * To use strobes, redefine the macros SER_STROBE_ON, - * SER_STROBE_OFF and SER_STROBE_INIT and set - * CONFIG_SER_STROBE to 1. - */ -#if !defined(CONFIG_SER_STROBE) || !CONFIG_SER_STROBE - #define SER_STROBE_ON do {/*nop*/} while(0) - #define SER_STROBE_OFF do {/*nop*/} while(0) - #define SER_STROBE_INIT do {/*nop*/} while(0) -#endif - - /* From the high-level serial driver */ -extern struct Serial ser_handles[SER_CNT]; +extern struct Serial *ser_handles[SER_CNT]; /* TX and RX buffers */ static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE]; @@ -340,20 +324,6 @@ struct AvrSerial }; -/* - * These are to trick GCC into *not* using absolute addressing mode - * when accessing ser_handles, which is very expensive. - * - * Accessing through these pointers generates much shorter - * (and hopefully faster) code. - */ -struct Serial *ser_uart0 = &ser_handles[SER_UART0]; -#if AVR_HAS_UART1 -struct Serial *ser_uart1 = &ser_handles[SER_UART1]; -#endif -struct Serial *ser_spi = &ser_handles[SER_SPI]; - - /* * Callbacks @@ -391,7 +361,7 @@ static void uart0_enabletxirq(struct SerialHardware *_hw) static void uart0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate) { /* Compute baud-rate period */ - uint16_t period = DIV_ROUND(CLOCK_FREQ / 16UL, rate) - 1; + uint16_t period = DIV_ROUND(CPU_FREQ / 16UL, rate) - 1; #if !CPU_AVR_ATMEGA103 UBRR0H = (period) >> 8; @@ -444,7 +414,7 @@ static void uart1_enabletxirq(struct SerialHardware *_hw) static void uart1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate) { /* Compute baud-rate period */ - uint16_t period = DIV_ROUND(CLOCK_FREQ / 16UL, rate) - 1; + uint16_t period = DIV_ROUND(CPU_FREQ / 16UL, rate) - 1; UBRR1H = (period) >> 8; UBRR1L = (period); @@ -484,7 +454,7 @@ static void spi_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct * - as input but tied high forever! * This driver set the pin as output. */ - #warning SPI SS pin set as output for proper operation, check schematics for possible conflicts. + #warning FIXME:SPI SS pin set as output for proper operation, check schematics for possible conflicts. ATOMIC(SPI_DDR |= BV(SPI_SS_BIT)); ATOMIC(SPI_DDR &= ~BV(SPI_MISO_BIT)); @@ -547,14 +517,14 @@ static void spi_starttx(struct SerialHardware *_hw) { struct AvrSerial *hw = (struct AvrSerial *)_hw; - cpuflags_t flags; + cpu_flags_t flags; IRQ_SAVE_DISABLE(flags); /* Send data only if the SPI is not already transmitting */ - if (!hw->sending && !fifo_isempty(&ser_spi->txfifo)) + if (!hw->sending && !fifo_isempty(&ser_handles[SER_SPI]->txfifo)) { hw->sending = true; - SPDR = fifo_pop(&ser_spi->txfifo); + SPDR = fifo_pop(&ser_handles[SER_SPI]->txfifo); } IRQ_RESTORE(flags); @@ -675,10 +645,10 @@ struct SerialHardware *ser_hw_getdesc(int unit) #if CONFIG_SER_HWHANDSHAKE /// This interrupt is triggered when the CTS line goes high -SIGNAL(SIG_CTS) +DECLARE_ISR(SIG_CTS) { // Re-enable UDR empty interrupt and TX, then disable CTS interrupt - UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); + UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); EIMSK &= ~EIMSKF_CTS; } @@ -688,11 +658,11 @@ SIGNAL(SIG_CTS) /** * Serial 0 TX interrupt handler */ -SIGNAL(USART0_UDRE_vect) +DECLARE_ISR(USART0_UDRE_vect) { SER_STROBE_ON; - struct FIFOBuffer * const txfifo = &ser_uart0->txfifo; + struct FIFOBuffer * const txfifo = &ser_handles[SER_UART0]->txfifo; if (fifo_isempty(txfifo)) { @@ -706,7 +676,7 @@ SIGNAL(USART0_UDRE_vect) { // Disable rx interrupt and tx, enable CTS interrupt // UNTESTED - UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); + UCSR0B = BV(BIT_RXCIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); EIFR |= EIMSKF_CTS; EIMSK |= EIMSKF_CTS; } @@ -736,18 +706,18 @@ SIGNAL(USART0_UDRE_vect) * otherwise we'd stop the serial port with some data * still pending in the buffer. */ -SIGNAL(SIG_UART0_TRANS) +DECLARE_ISR(SIG_UART0_TRANS) { SER_STROBE_ON; - struct FIFOBuffer * const txfifo = &ser_uart0->txfifo; + struct FIFOBuffer * const txfifo = &ser_handles[SER_UART0]->txfifo; if (fifo_isempty(txfifo)) { SER_UART0_BUS_TXOFF; UARTDescs[SER_UART0].sending = false; } else - UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); + UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); SER_STROBE_OFF; } @@ -759,11 +729,11 @@ SIGNAL(SIG_UART0_TRANS) /** * Serial 1 TX interrupt handler */ -SIGNAL(USART1_UDRE_vect) +DECLARE_ISR(USART1_UDRE_vect) { SER_STROBE_ON; - struct FIFOBuffer * const txfifo = &ser_uart1->txfifo; + struct FIFOBuffer * const txfifo = &ser_handles[SER_UART1]->txfifo; if (fifo_isempty(txfifo)) { @@ -777,7 +747,7 @@ SIGNAL(USART1_UDRE_vect) { // Disable rx interrupt and tx, enable CTS interrupt // UNTESTED - UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); + UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); EIFR |= EIMSKF_CTS; EIMSK |= EIMSKF_CTS; } @@ -797,18 +767,18 @@ SIGNAL(USART1_UDRE_vect) * * \sa port 0 TX complete handler. */ -SIGNAL(SIG_UART1_TRANS) +DECLARE_ISR(USART1_TX_vect) { SER_STROBE_ON; - struct FIFOBuffer * const txfifo = &ser_uart1->txfifo; + struct FIFOBuffer * const txfifo = &ser_handles[SER_UART1]->txfifo; if (fifo_isempty(txfifo)) { SER_UART1_BUS_TXOFF; UARTDescs[SER_UART1].sending = false; } else - UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); + UCSR1B = BV(BIT_RXCIE1) | BV(BIT_UDRIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); SER_STROBE_OFF; } @@ -832,7 +802,7 @@ SIGNAL(SIG_UART1_TRANS) * RXCIE is cleared. Unfortunately the RXC flag is read-only * and can't be cleared by code. */ -SIGNAL(USART0_RX_vect) +DECLARE_ISR(USART0_RX_vect) { SER_STROBE_ON; @@ -841,17 +811,17 @@ SIGNAL(USART0_RX_vect) //IRQ_ENABLE; /* Should be read before UDR */ - ser_uart0->status |= UCSR0A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR); + ser_handles[SER_UART0]->status |= UCSR0A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR); /* To clear the RXC flag we must _always_ read the UDR even when we're * not going to accept the incoming data, otherwise a new interrupt * will occur once the handler terminates. */ char c = UDR0; - struct FIFOBuffer * const rxfifo = &ser_uart0->rxfifo; + struct FIFOBuffer * const rxfifo = &ser_handles[SER_UART0]->rxfifo; if (fifo_isfull(rxfifo)) - ser_uart0->status |= SERRF_RXFIFOOVERRUN; + ser_handles[SER_UART0]->status |= SERRF_RXFIFOOVERRUN; else { fifo_push(rxfifo, c); @@ -880,9 +850,9 @@ SIGNAL(USART0_RX_vect) * is heavily loaded, because an interrupt could be retriggered * when executing the handler prologue before RXCIE is disabled. * - * \see SIGNAL(USART1_RX_vect) + * \see DECLARE_ISR(USART1_RX_vect) */ -SIGNAL(USART1_RX_vect) +DECLARE_ISR(USART1_RX_vect) { SER_STROBE_ON; @@ -891,17 +861,17 @@ SIGNAL(USART1_RX_vect) //IRQ_ENABLE; /* Should be read before UDR */ - ser_uart1->status |= UCSR1A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR); + ser_handles[SER_UART1]->status |= UCSR1A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR); /* To avoid an IRQ storm, we must _always_ read the UDR even when we're * not going to accept the incoming data */ char c = UDR1; - struct FIFOBuffer * const rxfifo = &ser_uart1->rxfifo; + struct FIFOBuffer * const rxfifo = &ser_handles[SER_UART1]->rxfifo; //ASSERT_VALID_FIFO(rxfifo); if (UNLIKELY(fifo_isfull(rxfifo))) - ser_uart1->status |= SERRF_RXFIFOOVERRUN; + ser_handles[SER_UART1]->status |= SERRF_RXFIFOOVERRUN; else { fifo_push(rxfifo, c); @@ -923,22 +893,22 @@ SIGNAL(USART1_RX_vect) /** * SPI interrupt handler */ -SIGNAL(SIG_SPI) +DECLARE_ISR(SIG_SPI) { SER_STROBE_ON; /* Read incoming byte. */ - if (!fifo_isfull(&ser_spi->rxfifo)) - fifo_push(&ser_spi->rxfifo, SPDR); + if (!fifo_isfull(&ser_handles[SER_SPI]->rxfifo)) + fifo_push(&ser_handles[SER_SPI]->rxfifo, SPDR); /* * FIXME else - ser_spi->status |= SERRF_RXFIFOOVERRUN; + ser_handles[SER_SPI]->status |= SERRF_RXFIFOOVERRUN; */ /* Send */ - if (!fifo_isempty(&ser_spi->txfifo)) - SPDR = fifo_pop(&ser_spi->txfifo); + if (!fifo_isempty(&ser_handles[SER_SPI]->txfifo)) + SPDR = fifo_pop(&ser_handles[SER_SPI]->txfifo); else UARTDescs[SER_SPI].sending = false;