X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Favr%2Fdrv%2Fser_avr.c;h=ee6c6ab10437052ebd977f57a32be1909ff419cd;hb=74081ebc421ca63e090ae8027a634a0c1b8f6864;hp=11a6c65c024c7d628f5041056d556d238eeab21e;hpb=6be047844350e6988c1a82a68ff8572fb2b60b57;p=bertos.git

diff --git a/bertos/cpu/avr/drv/ser_avr.c b/bertos/cpu/avr/drv/ser_avr.c
index 11a6c65c..ee6c6ab1 100644
--- a/bertos/cpu/avr/drv/ser_avr.c
+++ b/bertos/cpu/avr/drv/ser_avr.c
@@ -1080,22 +1080,6 @@ DECLARE_ISR(USART2_UDRE_vect)
 		UARTDescs[SER_UART2].sending = false;
 #endif
 	}
-
-/**
- * ATMEGA64, 128 and 103 do not have more than 2 USARTs
-
-#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
-	else if (!IS_CTS_ON)
-	{
-		// Disable rx interrupt and tx, enable CTS interrupt
-		// UNTESTED
-		UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1);
-		EIFR |= EIMSKF_CTS;
-		EIMSK |= EIMSKF_CTS;
-	}
-#endif
-
- */
 	else
 	{
 		char c = fifo_pop(txfifo);
@@ -1148,22 +1132,6 @@ DECLARE_ISR(USART3_UDRE_vect)
 		UARTDescs[SER_UART3].sending = false;
 #endif
 	}
-
-/**
- * ATMEGA64, 128 and 103 do not have more than 2 USARTs
-
-#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
-	else if (!IS_CTS_ON)
-	{
-		// Disable rx interrupt and tx, enable CTS interrupt
-		// UNTESTED
-		UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1);
-		EIFR |= EIMSKF_CTS;
-		EIMSK |= EIMSKF_CTS;
-	}
-#endif
-
- */
 	else
 	{
 		char c = fifo_pop(txfifo);