X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fcortex-m3%2Fdrv%2Fadc_stm32.c;h=10ee143e90912c3b596201766c68fceeaa38bc19;hb=563795df4180aaceb7d69306551230c98fbca879;hp=ed17ec1008b74c362018b2a7d00550cf74c2b44c;hpb=f3058b1ad80e751f3d9fd0664eaf44c3a41c1298;p=bertos.git

diff --git a/bertos/cpu/cortex-m3/drv/adc_stm32.c b/bertos/cpu/cortex-m3/drv/adc_stm32.c
index ed17ec10..10ee143e 100644
--- a/bertos/cpu/cortex-m3/drv/adc_stm32.c
+++ b/bertos/cpu/cortex-m3/drv/adc_stm32.c
@@ -26,7 +26,7 @@
  * invalidate any other reasons why the executable file might be covered by
  * the GNU General Public License.
  *
- * Copyright 2008 Develer S.r.l. (http://www.develer.com/)
+ * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
  *
  * -->
  *
@@ -150,7 +150,7 @@ uint16_t adc_hw_read(void)
 		adc_process = NULL;
 		return ret;
 	#else
-		/* Wait in polling until is done */
+		/* Wait in polling until conversion is done */
 		while (!(adc->SR & BV(SR_EOC)));
 
 		/* Return the last converted data */
@@ -163,8 +163,6 @@ uint16_t adc_hw_read(void)
  */
 void adc_hw_init(void)
 {
-	/* Enable clocking on AFIO */
-	RCC->APB2ENR |= RCC_APB2_AFIO;
 	RCC->APB2ENR |= (RCC_APB2_GPIOA | RCC_APB2_GPIOB | RCC_APB2_GPIOC);
 	RCC->APB2ENR |= RCC_APB2_ADC1;
 
@@ -175,6 +173,13 @@ void adc_hw_init(void)
 	adc->SQR2 = 0;
 	adc->SQR3 = 0;
 
+	/* Calibrate ADC */
+	adc->CR2 |= BV(CR2_RTSCAL);
+	adc->CR2 |= BV(CR2_CAL);
+
+	/* Wait in polling until calibration is done */
+	while (adc->CR2 & BV(CR2_CAL));
+
 	/*
 	 * Configure ADC
 	 *  - Regular mode
@@ -183,12 +188,28 @@ void adc_hw_init(void)
 	 */
 	adc->CR2 |= (BV(CR2_ADON) | ADC_EXTERNALTRIGCONV_NONE | BV(CR2_TSVREFE));
 
-	/* Set 17.1usec sampling time on channel 16 and 17 */
-	adc->SMPR1 |= ((ADC_SAMPLETIME_239CYCLES5 << ADC_CHANNEL_16) |
-		(ADC_SAMPLETIME_239CYCLES5 << ADC_CHANNEL_17));
+	/* Set 17.1usec sampling time*/
+	adc->SMPR1 |= ((ADC_SAMPLETIME_239CYCLES5 << SMPR1_CH17) |
+		(ADC_SAMPLETIME_239CYCLES5 << SMPR1_CH16) |
+		(ADC_SAMPLETIME_239CYCLES5 << SMPR1_CH15) |
+		(ADC_SAMPLETIME_239CYCLES5 << SMPR1_CH14) |
+		(ADC_SAMPLETIME_239CYCLES5 << SMPR1_CH13) |
+		(ADC_SAMPLETIME_239CYCLES5 << SMPR1_CH12) |
+		(ADC_SAMPLETIME_239CYCLES5 << SMPR1_CH11) |
+		(ADC_SAMPLETIME_239CYCLES5 << SMPR1_CH10));
+
+	adc->SMPR2 |= ((ADC_SAMPLETIME_239CYCLES5 << SMPR2_CH9) |
+		(ADC_SAMPLETIME_239CYCLES5 << SMPR2_CH8) |
+		(ADC_SAMPLETIME_239CYCLES5 << SMPR2_CH7) |
+		(ADC_SAMPLETIME_239CYCLES5 << SMPR2_CH6) |
+		(ADC_SAMPLETIME_239CYCLES5 << SMPR2_CH5) |
+		(ADC_SAMPLETIME_239CYCLES5 << SMPR2_CH4) |
+		(ADC_SAMPLETIME_239CYCLES5 << SMPR2_CH3) |
+		(ADC_SAMPLETIME_239CYCLES5 << SMPR2_CH2) |
+		(ADC_SAMPLETIME_239CYCLES5 << SMPR2_CH1) |
+		(ADC_SAMPLETIME_239CYCLES5 << SMPR2_CH0));
 
 	#if CONFIG_KERN
 		adc_enable_irq();
 	#endif
-
 }