X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fcortex-m3%2Fdrv%2Fclock.c;fp=bertos%2Fcpu%2Fcortex-m3%2Fdrv%2Fclock.c;h=f3d31ec563fb28b45451dd25bb0454f11a3375ab;hb=49f2d09a180dc6e50dcc9f995fc2ba0ca3daea11;hp=3618185b0c585bb2f2de8a0635e815600528f760;hpb=e5ae58a13772adb3aad5cd50404efb18b3aca5a8;p=bertos.git

diff --git a/bertos/cpu/cortex-m3/drv/clock.c b/bertos/cpu/cortex-m3/drv/clock.c
index 3618185b..f3d31ec5 100644
--- a/bertos/cpu/cortex-m3/drv/clock.c
+++ b/bertos/cpu/cortex-m3/drv/clock.c
@@ -106,6 +106,7 @@ unsigned long clock_get_rate(void)
 void clock_set_rate(void)
 {
 	reg32_t rcc, rcc2;
+	unsigned long clk;
 	int i;
 
 	rcc = HWREG(SYSCTL_RCC);
@@ -158,14 +159,23 @@ void clock_set_rate(void)
 	 * frequency for the microcontroller.
 	 */
 	rcc &= ~(SYSCTL_RCC_SYSDIV_M | SYSCTL_RCC_USESYSDIV);
-	for (i = 0; i < 15; i++)
+
+	/*
+	 * Try to evaluate the correct SYSDIV value depending on the desired
+	 * CPU frequency.
+	 */
+	clk = RCC_TO_CLK(rcc);
+	for (i = 0; i < 16; i++)
 	{
-		if (CPU_FREQ == RCC_TO_CLK(rcc))
+		clk = clk / (i + 1);
+		if (CPU_FREQ >= clk)
 			break;
-		rcc |= SYSCTL_RCC_USESYSDIV;
 	}
 	if (i)
+	{
+		rcc |= SYSCTL_RCC_USESYSDIV;
 		rcc |= i << SYSCTL_RCC_SYSDIV_SHIFT;
+	}
 
 	/*
 	 * Step #4: wait for the PLL to lock by polling the PLLLRIS bit in the