X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fcortex-m3%2Fdrv%2Fclock_lm3s.c;h=0c79f8780c60017a4ce2673896c303b236aa9fdb;hb=7a562649d9bc6e42df079696410fff7091410656;hp=76e901bda6430b3ca3597de4b2d816fd1258a733;hpb=0a4053ecfc25acc4b20c527ec8019e57498eb2e7;p=bertos.git

diff --git a/bertos/cpu/cortex-m3/drv/clock_lm3s.c b/bertos/cpu/cortex-m3/drv/clock_lm3s.c
index 76e901bd..0c79f878 100644
--- a/bertos/cpu/cortex-m3/drv/clock_lm3s.c
+++ b/bertos/cpu/cortex-m3/drv/clock_lm3s.c
@@ -35,10 +35,13 @@
  * \author Andrea Righi <arighi@develer.com>
  */
 
+#include "clock_lm3s.h"
+
 #include <cfg/compiler.h>
 #include <cfg/debug.h>
+
 #include <io/lm3s.h>
-#include "clock_lm3s.h"
+
 
 /* The PLL VCO frequency is 400 MHz */
 #define PLL_VCO	400000000UL
@@ -62,7 +65,7 @@ void NAKED lm3s_busyWait(unsigned long iterations)
 		: : "r"(__n) : "memory", "cc");
 }
 
-unsigned long clock_get_rate(void)
+INLINE unsigned long clock_get_rate(void)
 {
 	reg32_t rcc = HWREG(SYSCTL_RCC);
 
@@ -88,12 +91,33 @@ INLINE int evaluate_sysdiv(unsigned long freq)
 	return i;
 }
 
-void clock_set_rate(void)
+void clock_init(void)
 {
 	reg32_t rcc, rcc2;
 	unsigned long clk;
 	int i;
 
+	/*
+	 * PLL may not function properly at default LDO setting.
+	 *
+	 * Description:
+	 *
+	 * In designs that enable and use the PLL module, unstable device
+	 * behavior may occur with the LDO set at its default of 2.5 volts or
+	 * below (minimum of 2.25 volts). Designs that do not use the PLL
+	 * module are not affected.
+	 *
+	 * Workaround: Prior to enabling the PLL module, it is recommended that
+	 * the default LDO voltage setting of 2.5 V be adjusted to 2.75 V using
+	 * the LDO Power Control (LDOPCTL) register.
+	 *
+	 * Silicon Revision Affected: A1, A2
+	 *
+	 * See also: Stellaris LM3S1968 A2 Errata documentation.
+	 */
+	if (REVISION_IS_A1 | REVISION_IS_A2)
+		HWREG(SYSCTL_LDOPCTL) = SYSCTL_LDOPCTL_2_75V;
+
 	rcc = HWREG(SYSCTL_RCC);
 	rcc2 = HWREG(SYSCTL_RCC2);