X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fcortex-m3%2Fdrv%2Fclock_lm3s.c;h=1c643b58c77cdc4599d729b64508e59b91333178;hb=ffc9d84f819c7480515ece4417329f4972510462;hp=8790b0e6ed69319fcdbf3f644a2417f0d199811a;hpb=692b24f898b31b95e639c0f43f225ed1726719d3;p=bertos.git

diff --git a/bertos/cpu/cortex-m3/drv/clock_lm3s.c b/bertos/cpu/cortex-m3/drv/clock_lm3s.c
index 8790b0e6..1c643b58 100644
--- a/bertos/cpu/cortex-m3/drv/clock_lm3s.c
+++ b/bertos/cpu/cortex-m3/drv/clock_lm3s.c
@@ -51,12 +51,15 @@
 /*
  * Very small delay: each loop takes 3 cycles.
  */
-INLINE void __delay(unsigned long iterations)
+void NAKED __delay(unsigned long iterations)
 {
+	register uint32_t __n asm("r0") = iterations;
+
 	asm volatile (
-		"1:	subs	%0, #1\n\t"
-		"	bne 1b\n\t"
-		: "=r"(iterations) : : "memory", "cc");
+		"1: subs r0, #1\n\t"
+		"bne 1b\n\t"
+		"bx lr\n\t"
+		: : "r"(__n) : "memory", "cc");
 }
 
 unsigned long clock_get_rate(void)
@@ -110,6 +113,8 @@ void clock_set_rate(void)
 	HWREG(SYSCTL_RCC) = rcc;
 	HWREG(SYSCTL_RCC) = rcc2;
 
+	__delay(16);
+
 	/*
 	 * Step #2: select the crystal value (XTAL) and oscillator source
 	 * (OSCSRC), and clear the PWRDN bit in RCC/RCC2. Setting the XTAL