X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fcortex-m3%2Fdrv%2Fclock_lm3s.c;h=df4681ea3ef860b9c62d5cce8713c07c8722cb2c;hb=6be047844350e6988c1a82a68ff8572fb2b60b57;hp=1c643b58c77cdc4599d729b64508e59b91333178;hpb=ad984bef9a7d5ca01b97eb8b14a655e64ea79cc9;p=bertos.git

diff --git a/bertos/cpu/cortex-m3/drv/clock_lm3s.c b/bertos/cpu/cortex-m3/drv/clock_lm3s.c
index 1c643b58..df4681ea 100644
--- a/bertos/cpu/cortex-m3/drv/clock_lm3s.c
+++ b/bertos/cpu/cortex-m3/drv/clock_lm3s.c
@@ -35,10 +35,13 @@
  * \author Andrea Righi <arighi@develer.com>
  */
 
+#include "clock_lm3s.h"
+
 #include <cfg/compiler.h>
 #include <cfg/debug.h>
-#include "io/lm3s.h"
-#include "clock_lm3s.h"
+
+#include <io/lm3s.h>
+
 
 /* The PLL VCO frequency is 400 MHz */
 #define PLL_VCO	400000000UL
@@ -51,7 +54,7 @@
 /*
  * Very small delay: each loop takes 3 cycles.
  */
-void NAKED __delay(unsigned long iterations)
+void NAKED lm3s_busyWait(unsigned long iterations)
 {
 	register uint32_t __n asm("r0") = iterations;
 
@@ -62,7 +65,7 @@ void NAKED __delay(unsigned long iterations)
 		: : "r"(__n) : "memory", "cc");
 }
 
-unsigned long clock_get_rate(void)
+INLINE unsigned long clock_get_rate(void)
 {
 	reg32_t rcc = HWREG(SYSCTL_RCC);
 
@@ -88,7 +91,7 @@ INLINE int evaluate_sysdiv(unsigned long freq)
 	return i;
 }
 
-void clock_set_rate(void)
+void clock_init(void)
 {
 	reg32_t rcc, rcc2;
 	unsigned long clk;
@@ -113,7 +116,7 @@ void clock_set_rate(void)
 	HWREG(SYSCTL_RCC) = rcc;
 	HWREG(SYSCTL_RCC) = rcc2;
 
-	__delay(16);
+	lm3s_busyWait(16);
 
 	/*
 	 * Step #2: select the crystal value (XTAL) and oscillator source
@@ -139,7 +142,7 @@ void clock_set_rate(void)
         HWREG(SYSCTL_RCC) = rcc;
 	HWREG(SYSCTL_RCC) = rcc2;
 
-	__delay(16);
+	lm3s_busyWait(16);
 
 	/*
 	 * Step #3: select the desired system divider (SYSDIV) in RCC/RCC2 and
@@ -171,5 +174,5 @@ void clock_set_rate(void)
 
 	HWREG(SYSCTL_RCC) = rcc;
 
-	__delay(16);
+	lm3s_busyWait(16);
 }