X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fcortex-m3%2Fdrv%2Fclock_sam3.c;h=55173e62acd7e30411c19448f23b5b753b5d4449;hb=63dca689018786e2dedba8683dc230b8abd82c98;hp=b0486c51d992ef94edcf16a7e60e4e382ee09a53;hpb=bce79ae17dc4b489639cd102fa7563acd129898f;p=bertos.git

diff --git a/bertos/cpu/cortex-m3/drv/clock_sam3.c b/bertos/cpu/cortex-m3/drv/clock_sam3.c
index b0486c51..55173e62 100644
--- a/bertos/cpu/cortex-m3/drv/clock_sam3.c
+++ b/bertos/cpu/cortex-m3/drv/clock_sam3.c
@@ -30,16 +30,15 @@
  *
  * -->
  *
- * \brief ATSAM3 clock setup.
+ * \brief Atmel SAM3 clock setup.
  *
  * \author Stefano Fedrigo <aleph@develer.com>
  */
 
 #include "clock_sam3.h"
-#include <io/sam3_pmc.h>
-#include <io/sam3_sysctl.h>
 #include <cfg/compiler.h>
 #include <cfg/macros.h>
+#include <io/sam3.h>
 
 
 /* Frequency of board main oscillator */
@@ -90,40 +89,49 @@ void clock_init(void)
 {
 	uint32_t timeout;
 
+	/* Disable watchdog */
+	WDT_MR = BV(WDT_WDDIS);
+
+	/* Set 4 wait states for flash access, needed for higher CPU clock rates */
+	EEFC_FMR = EEFC_FMR_FWS(3);
+
 	// Select external slow clock
-	if (!(SUPC_SR_R & SUPC_SR_OSCSEL))
+	if (!(SUPC_SR & BV(SUPC_SR_OSCSEL)))
 	{
-		SUPC_CR_R = SUPC_CR_XTALSEL | SUPC_CR_KEY(0xA5);
-		while (!(SUPC_SR_R & SUPC_SR_OSCSEL));
+		SUPC_CR = BV(SUPC_CR_XTALSEL) | SUPC_CR_KEY(0xA5);
+		while (!(SUPC_SR & BV(SUPC_SR_OSCSEL)));
 	}
 
 	// Initialize main oscillator
-	if (!(CKGR_MOR_R & CKGR_MOR_MOSCSEL))
+	if (!(CKGR_MOR & BV(CKGR_MOR_MOSCSEL)))
 	{
-		CKGR_MOR_R = CKGR_MOR_KEY(0x37) | BOARD_OSC_COUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
+		CKGR_MOR = CKGR_MOR_KEY(0x37) | BOARD_OSC_COUNT | BV(CKGR_MOR_MOSCRCEN) | BV(CKGR_MOR_MOSCXTEN);
 		timeout = CLOCK_TIMEOUT;
-		while (!(PMC_SR_R & PMC_SR_MOSCXTS) && --timeout);
+		while (!(PMC_SR & BV(PMC_SR_MOSCXTS)) && --timeout);
 	}
 
 	// Switch to external oscillator
-	CKGR_MOR_R = CKGR_MOR_KEY(0x37) | BOARD_OSC_COUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
+	CKGR_MOR = CKGR_MOR_KEY(0x37) | BOARD_OSC_COUNT | BV(CKGR_MOR_MOSCRCEN) | BV(CKGR_MOR_MOSCXTEN) | BV(CKGR_MOR_MOSCSEL);
 	timeout = CLOCK_TIMEOUT;
-	while (!(PMC_SR_R & PMC_SR_MOSCSELS) && --timeout);
+	while (!(PMC_SR & BV(PMC_SR_MOSCSELS)) && --timeout);
 
-	PMC_MCKR_R = (PMC_MCKR_R & ~(uint32_t)PMC_MCKR_CSS_M) | PMC_MCKR_CSS_MAIN_CLK;
+	PMC_MCKR = (PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_MASK) | PMC_MCKR_CSS_MAIN_CLK;
 	timeout = CLOCK_TIMEOUT;
-	while (!(PMC_SR_R & PMC_SR_MCKRDY) && --timeout);
+	while (!(PMC_SR & BV(PMC_SR_MCKRDY)) && --timeout);
 
 	// Initialize and enable PLL clock
-	CKGR_PLLR_R = evaluate_pll() | CKGR_PLLR_STUCKTO1 | CKGR_PLLR_PLLCOUNT(0x1);
+	CKGR_PLLR = evaluate_pll() | BV(CKGR_PLLR_STUCKTO1) | CKGR_PLLR_PLLCOUNT(0x1);
 	timeout = CLOCK_TIMEOUT;
-	while (!(PMC_SR_R & PMC_SR_LOCK) && --timeout);
+	while (!(PMC_SR & BV(PMC_SR_LOCK)) && --timeout);
 
-	PMC_MCKR_R = PMC_MCKR_CSS_MAIN_CLK;
+	PMC_MCKR = PMC_MCKR_CSS_MAIN_CLK;
 	timeout = CLOCK_TIMEOUT;
-	while (!(PMC_SR_R & PMC_SR_MCKRDY) && --timeout);
+	while (!(PMC_SR & BV(PMC_SR_MCKRDY)) && --timeout);
 
-	PMC_MCKR_R = PMC_MCKR_CSS_PLL_CLK;
+	PMC_MCKR = PMC_MCKR_CSS_PLL_CLK;
 	timeout = CLOCK_TIMEOUT;
-	while (!(PMC_SR_R & PMC_SR_MCKRDY) && --timeout);
+	while (!(PMC_SR & BV(PMC_SR_MCKRDY)) && --timeout);
+
+	/* Enable clock on PIO for inputs */
+	PMC_PCER = BV(PIOA_ID) | BV(PIOB_ID) | BV(PIOC_ID);
 }