X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fcortex-m3%2Fdrv%2Fclock_sam3.c;h=fcb46c4b29dd06c5454eebf8ad05366e10848abb;hb=f81df2ee3de292493462ee9d0a8905eaafb57243;hp=b0486c51d992ef94edcf16a7e60e4e382ee09a53;hpb=bce79ae17dc4b489639cd102fa7563acd129898f;p=bertos.git

diff --git a/bertos/cpu/cortex-m3/drv/clock_sam3.c b/bertos/cpu/cortex-m3/drv/clock_sam3.c
index b0486c51..fcb46c4b 100644
--- a/bertos/cpu/cortex-m3/drv/clock_sam3.c
+++ b/bertos/cpu/cortex-m3/drv/clock_sam3.c
@@ -30,37 +30,43 @@
  *
  * -->
  *
- * \brief ATSAM3 clock setup.
+ * \brief Atmel SAM3 clock setup.
  *
  * \author Stefano Fedrigo <aleph@develer.com>
  */
 
 #include "clock_sam3.h"
-#include <io/sam3_pmc.h>
-#include <io/sam3_sysctl.h>
 #include <cfg/compiler.h>
 #include <cfg/macros.h>
+#include <io/sam3.h>
 
 
 /* Frequency of board main oscillator */
 #define BOARDOSC_FREQ  12000000
 
-/* Main crystal oscillator startup time, optimal value for CPU_FREQ == 48 MHz */
-#define BOARD_OSC_COUNT  (CKGR_MOR_MOSCXTST(0x8))
-
 /* Timer countdown timeout for clock initialization operations */
 #define CLOCK_TIMEOUT    0xFFFFFFFF
 
 
+#if CPU_FREQ == 84000000 || CPU_FREQ == 48000000
+
+INLINE uint32_t evaluate_pll(void)
+{
+	return CKGR_PLLR_MUL(CPU_FREQ / BOARDOSC_FREQ * 2 - 1) | CKGR_PLLR_DIV(2);
+}
+
+#else
+
+#warning CPU clock frequency non-standard setting: multiplier and divider values \
+ will be computed at runtime: effective computed frequency could be different \
+ from expected.
+
 /*
  * Try to evaluate the correct divider and multiplier value depending
  * on the desired CPU frequency.
  *
  * We try all combinations in a certain range of divider and multiplier
- * values.  The range can change, with better match with "strange"
- * frequencies, but boot time will be longer.
- *
- * Limits for SAM3N: divider [1,255], multiplier [1,2047].
+ * values.  Start with higher multipliers and divisors, generally better.
  */
 INLINE uint32_t evaluate_pll(void)
 {
@@ -68,9 +74,9 @@ INLINE uint32_t evaluate_pll(void)
 	int best_delta = CPU_FREQ;
 	int freq = 0;
 
-	for (mul = 1; mul <= 8; mul++)
+	for (mul = 13; mul > 0; mul--)
 	{
-		for (div = 1; div <= 24; div++)
+		for (div = 24; div > 0; div--)
 		{
 			freq = BOARDOSC_FREQ / div * (1 + mul);
 			if (ABS((int)CPU_FREQ - freq) < best_delta) {
@@ -81,49 +87,60 @@ INLINE uint32_t evaluate_pll(void)
 		}
 	}
 
-	// Bit 29 must always be set to 1
-	return CKGR_PLLR_DIV(best_div) | CKGR_PLLR_MUL(best_mul) | BV(29);
+	return CKGR_PLLR_DIV(best_div) | CKGR_PLLR_MUL(best_mul);
 }
 
+#endif /* CPU_FREQ */
 
 void clock_init(void)
 {
 	uint32_t timeout;
 
-	// Select external slow clock
-	if (!(SUPC_SR_R & SUPC_SR_OSCSEL))
-	{
-		SUPC_CR_R = SUPC_CR_XTALSEL | SUPC_CR_KEY(0xA5);
-		while (!(SUPC_SR_R & SUPC_SR_OSCSEL));
-	}
+	/* Disable watchdog */
+	WDT_MR = BV(WDT_WDDIS);
+
+	/* Set wait states for flash access, needed for higher CPU clock rates */
+	EEFC0_FMR = EEFC_FMR_FWS(3);
+#ifdef EEFC1_FMR
+	EEFC1_FMR = EEFC_FMR_FWS(3);
+#endif
 
 	// Initialize main oscillator
-	if (!(CKGR_MOR_R & CKGR_MOR_MOSCSEL))
+	if (!(CKGR_MOR & BV(CKGR_MOR_MOSCSEL)))
 	{
-		CKGR_MOR_R = CKGR_MOR_KEY(0x37) | BOARD_OSC_COUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
+		CKGR_MOR = CKGR_MOR_KEY(0x37) | CKGR_MOR_MOSCXTST(0x8)
+			| BV(CKGR_MOR_MOSCRCEN) | BV(CKGR_MOR_MOSCXTEN);
 		timeout = CLOCK_TIMEOUT;
-		while (!(PMC_SR_R & PMC_SR_MOSCXTS) && --timeout);
+		while (!(PMC_SR & BV(PMC_SR_MOSCXTS)) && --timeout);
 	}
 
 	// Switch to external oscillator
-	CKGR_MOR_R = CKGR_MOR_KEY(0x37) | BOARD_OSC_COUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
-	timeout = CLOCK_TIMEOUT;
-	while (!(PMC_SR_R & PMC_SR_MOSCSELS) && --timeout);
-
-	PMC_MCKR_R = (PMC_MCKR_R & ~(uint32_t)PMC_MCKR_CSS_M) | PMC_MCKR_CSS_MAIN_CLK;
+	CKGR_MOR = CKGR_MOR_KEY(0x37) | CKGR_MOR_MOSCXTST(0x8)
+		| BV(CKGR_MOR_MOSCRCEN) | BV(CKGR_MOR_MOSCXTEN) | BV(CKGR_MOR_MOSCSEL);
 	timeout = CLOCK_TIMEOUT;
-	while (!(PMC_SR_R & PMC_SR_MCKRDY) && --timeout);
+	while (!(PMC_SR & BV(PMC_SR_MOSCXTS)) && --timeout);
 
 	// Initialize and enable PLL clock
-	CKGR_PLLR_R = evaluate_pll() | CKGR_PLLR_STUCKTO1 | CKGR_PLLR_PLLCOUNT(0x1);
+	CKGR_PLLR = evaluate_pll() | BV(CKGR_PLLR_STUCKTO1) | CKGR_PLLR_PLLCOUNT(0x2);
 	timeout = CLOCK_TIMEOUT;
-	while (!(PMC_SR_R & PMC_SR_LOCK) && --timeout);
+	while (!(PMC_SR & BV(PMC_SR_LOCK)) && --timeout);
 
-	PMC_MCKR_R = PMC_MCKR_CSS_MAIN_CLK;
+	PMC_MCKR = PMC_MCKR_CSS_MAIN_CLK;
 	timeout = CLOCK_TIMEOUT;
-	while (!(PMC_SR_R & PMC_SR_MCKRDY) && --timeout);
+	while (!(PMC_SR & BV(PMC_SR_MCKRDY)) && --timeout);
 
-	PMC_MCKR_R = PMC_MCKR_CSS_PLL_CLK;
+	PMC_MCKR = PMC_MCKR_CSS_PLL_CLK;
 	timeout = CLOCK_TIMEOUT;
-	while (!(PMC_SR_R & PMC_SR_MCKRDY) && --timeout);
+	while (!(PMC_SR & BV(PMC_SR_MCKRDY)) && --timeout);
+
+	/* Enable clock on PIO for inputs */
+	// TODO: move this in gpio_init() for better power management?
+	pmc_periphEnable(PIOA_ID);
+	pmc_periphEnable(PIOB_ID);
+	pmc_periphEnable(PIOC_ID);
+#ifdef PIOF_ID
+	pmc_periphEnable(PIOD_ID);
+	pmc_periphEnable(PIOE_ID);
+	pmc_periphEnable(PIOF_ID);
+#endif
 }