X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fcortex-m3%2Fdrv%2Fclock_stm32.c;h=4b8cd89897de9982210badca6b9ccf3d5eefacc3;hb=dc9b8ecb40cb399616ef3044b7c1b29cf9cf76b4;hp=20959595a05fe803dbd144b3beff50e2c2cb5f17;hpb=50f291725e77a72e120af2e6136e8c1092b4aaaa;p=bertos.git

diff --git a/bertos/cpu/cortex-m3/drv/clock_stm32.c b/bertos/cpu/cortex-m3/drv/clock_stm32.c
index 20959595..4b8cd898 100644
--- a/bertos/cpu/cortex-m3/drv/clock_stm32.c
+++ b/bertos/cpu/cortex-m3/drv/clock_stm32.c
@@ -71,7 +71,7 @@ INLINE uint16_t pll_clock(void)
 	/* Hopefully this is evaluate at compile time... */
 	for (div = 2; div; div--)
 		for (mul = 2; mul <= 16; mul++)
-			if (CPU_FREQ >= (PLL_VCO / div * mul))
+			if (CPU_FREQ <= (PLL_VCO / div * mul))
 				break;
 	return mul << 8 | div;
 }
@@ -126,8 +126,23 @@ void clock_init(void)
 	rcc_pll_config();
 	while(!rcc_get_flag_status(RCC_FLAG_PLLRDY));
 
+	/* Configure USB clock (48MHz) */
+	*CFGR_USBPRE_BB = RCC_USBCLK_PLLCLK_1DIV5;
+	/* Configure ADC clock: PCLK2 (9MHz) */
+	RCC->CFGR &= CFGR_ADCPRE_RESET_MASK;
+	RCC->CFGR |= RCC_PCLK2_DIV8;
+	/* Configure system clock dividers: PCLK2 (72MHz) */
+	RCC->CFGR &= CFGR_PPRE2_RESET_MASK;
+	RCC->CFGR |= RCC_HCLK_DIV1 << 3;
+	/* Configure system clock dividers: PCLK1 (36MHz) */
+	RCC->CFGR &= CFGR_PPRE1_RESET_MASK;
+	RCC->CFGR |= RCC_HCLK_DIV2 << 3;
+	/* Configure system clock dividers: HCLK */
+	RCC->CFGR &= CFGR_HPRE_RESET_MASK;
+	RCC->CFGR |= RCC_SYSCLK_DIV1;
+
 	/* Set 1 wait state for the flash memory */
-	*(reg32_t *)0x40022000 = 0x12;
+	*(reg32_t *)FLASH_BASE = 0x12;
 
 	/* Clock the system from the PLL */
 	rcc_set_clock_source(RCC_SYSCLK_PLLCLK);