X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fcortex-m3%2Fdrv%2Fclock_stm32.c;h=8e9e86d0b5c775f041917e1b2f6172cce7961b81;hb=c23a8ab05fbdc06cd0881a88461b56f4f93dbbba;hp=4b8cd89897de9982210badca6b9ccf3d5eefacc3;hpb=dc9b8ecb40cb399616ef3044b7c1b29cf9cf76b4;p=bertos.git

diff --git a/bertos/cpu/cortex-m3/drv/clock_stm32.c b/bertos/cpu/cortex-m3/drv/clock_stm32.c
index 4b8cd898..8e9e86d0 100644
--- a/bertos/cpu/cortex-m3/drv/clock_stm32.c
+++ b/bertos/cpu/cortex-m3/drv/clock_stm32.c
@@ -66,7 +66,7 @@ INLINE int rcc_get_flag_status(uint32_t flag)
 
 INLINE uint16_t pll_clock(void)
 {
-	int div, mul;
+	unsigned int div, mul;
 
 	/* Hopefully this is evaluate at compile time... */
 	for (div = 2; div; div--)
@@ -136,7 +136,7 @@ void clock_init(void)
 	RCC->CFGR |= RCC_HCLK_DIV1 << 3;
 	/* Configure system clock dividers: PCLK1 (36MHz) */
 	RCC->CFGR &= CFGR_PPRE1_RESET_MASK;
-	RCC->CFGR |= RCC_HCLK_DIV2 << 3;
+	RCC->CFGR |= RCC_HCLK_DIV2;
 	/* Configure system clock dividers: HCLK */
 	RCC->CFGR &= CFGR_HPRE_RESET_MASK;
 	RCC->CFGR |= RCC_SYSCLK_DIV1;