X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fcortex-m3%2Fdrv%2Feth_sam3.h;h=7ed89bd57feb4ee3f181e05976c1f7ecc8dd1faa;hb=b7165529c0174f9bc5a1f4f51a4e405f202e48d5;hp=f733df9a4afd38244b2a8f3aa61dd0c9b943e2eb;hpb=72b2dafe03e2095ff62690b809b633024bc49fc4;p=bertos.git

diff --git a/bertos/cpu/cortex-m3/drv/eth_sam3.h b/bertos/cpu/cortex-m3/drv/eth_sam3.h
index f733df9a..7ed89bd5 100644
--- a/bertos/cpu/cortex-m3/drv/eth_sam3.h
+++ b/bertos/cpu/cortex-m3/drv/eth_sam3.h
@@ -42,9 +42,9 @@
 
 // Settings and definition for DAVICOM 9161A
 // \{
-#define NIC_PHY_ADDR            31
+#define NIC_PHY_ADDR            0
 
-//Registry definition
+// Register bits definition
 #define NIC_PHY_BMCR            0x00    //  Basic mode control register.
 #define NIC_PHY_BMCR_COLTEST    0x0080  //  Collision test.
 #define NIC_PHY_BMCR_FDUPLEX    0x0100  //  Full duplex mode.
@@ -61,6 +61,11 @@
 #define NIC_PHY_BMSR_ANEGCAPABLE 0x0008  // Able to do auto-negotiation
 #define NIC_PHY_BMSR_LINKSTAT   0x0004  //  Link status.
 
+#define NIC_PHY_ANLPAR_10_HDX   BV(5)   //  10BASE-T half duplex
+#define NIC_PHY_ANLPAR_10_FDX   BV(6)   //  10BASE-T full duplex
+#define NIC_PHY_ANLPAR_TX_HDX   BV(7)   //  100BASE-TX half duplex
+#define NIC_PHY_ANLPAR_TX_FDX   BV(8)   //  100BASE-TX full duplex
+
 #define NIC_PHY_ID1             0x02    //  PHY identifier register 1.
 #define NIC_PHY_ID2             0x03    //  PHY identifier register 2.
 #define NIC_PHY_ANAR            0x04    //  Auto negotiation advertisement register.
@@ -74,7 +79,6 @@
  * See schematics for AT91SAM7X-EK evalution board.
  */
 // All pins in port B
-#define PHY_TXCLK_ISOLATE_BIT   0
 #define PHY_REFCLK_XT2_BIT      0
 #define PHY_TXEN_BIT            1
 #define PHY_TXD0_BIT            2
@@ -123,7 +127,6 @@
  * See schematics for SAM3X-EK evalution board.
  */
 // Port B
-#define PHY_TXCLK_ISOLATE_BIT   0
 #define PHY_REFCLK_XT2_BIT      0
 #define PHY_TXEN_BIT            1
 #define PHY_TXD0_BIT            2
@@ -137,12 +140,11 @@
 // Port A
 #define PHY_MDINTR_BIT          5
 
-#define PHY_MII_PINS \
+#define PHY_MII_PINS_PORTB \
 	BV(PHY_REFCLK_XT2_BIT) \
 	| BV(PHY_TXEN_BIT) \
 	| BV(PHY_TXD0_BIT) \
 	| BV(PHY_TXD1_BIT) \
-	| BV(PHY_RXDV_TESTMODE_BIT) \
 	| BV(PHY_RXD0_AD0_BIT) \
 	| BV(PHY_RXD1_AD1_BIT) \
 	| BV(PHY_RXER_RXD4_RPTR_BIT) \