X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fcortex-m3%2Fdrv%2Fhsmci_sam3.c;h=b0c0ad0af522693a3afc08a548ee997352e4298d;hb=5bf8282a6c67268fd97cb7e8f6a1a6a52ddcc532;hp=13b2f1367940f033cde1202e68edc28a86b41c22;hpb=8a6460473f0a31c528617ffde51aa88985725c7a;p=bertos.git diff --git a/bertos/cpu/cortex-m3/drv/hsmci_sam3.c b/bertos/cpu/cortex-m3/drv/hsmci_sam3.c index 13b2f136..b0c0ad0a 100644 --- a/bertos/cpu/cortex-m3/drv/hsmci_sam3.c +++ b/bertos/cpu/cortex-m3/drv/hsmci_sam3.c @@ -36,99 +36,141 @@ #include "hsmci_sam3.h" +#include "hw/hw_sd.h" #include -#include #include +#include -#include +#include +#include +#include -#define HSMCI_INIT_SPEED 400000 -#define HSMCI_CLK_DIV ((CPU_FREQ / (HSMCI_INIT_SPEED << 1)) - 1) -#define HSMCI_ERROR_MASK (BV(HSMCI_SR_RINDE) | \ - BV(HSMCI_SR_RDIRE) | \ - BV(HSMCI_SR_RCRCE) | \ - BV(HSMCI_SR_RENDE) | \ - BV(HSMCI_SR_RTOE) | \ - BV(HSMCI_SR_DCRCE) | \ - BV(HSMCI_SR_DTOE) | \ - BV(HSMCI_SR_CSTOE) | \ - BV(HSMCI_SR_BLKOVRE) | \ - BV(HSMCI_SR_ACKRCVE)) +#define HSMCI_CLK_DIV(RATE) ((CPU_FREQ / (RATE << 1)) - 1) #define HSMCI_RESP_ERROR_MASK (BV(HSMCI_SR_RINDE) | BV(HSMCI_SR_RDIRE) \ - | BV(HSMCI_SR_RCRCE)| BV(HSMCI_SR_RENDE)| BV(HSMCI_SR_RTOE)) + | BV(HSMCI_SR_RENDE)| BV(HSMCI_SR_RTOE)) +#define HSMCI_DATA_ERROR_MASK (BV(HSMCI_SR_DCRCE) | BV(HSMCI_SR_DTOE)) +#define HSMCI_READY_MASK (BV(HSMCI_SR_CMDRDY) | BV(HSMCI_SR_NOTBUSY)) #define HSMCI_WAIT()\ do { \ cpu_relax(); \ - } while (!(HSMCI_SR & (BV(HSMCI_SR_CMDRDY) | BV(HSMCI_SR_NOTBUSY) | BV(HSMCI_SR_XFRDONE)))) + } while (!(HSMCI_SR & BV(HSMCI_SR_CMDRDY))) -#define HSMCI_ERROR() (HSMCI_SR & HSMCI_ERROR_MASK) -#define HSMCI_HW_INIT() \ -do { \ - PIOA_PDR = BV(19) | BV(20) | BV(21) | BV(22) | BV(23) | BV(24); \ - PIO_PERIPH_SEL(PIOA_BASE, BV(19) | BV(20) | BV(21) | BV(22) | BV(23) | BV(24), PIO_PERIPH_A); \ -} while (0) +#define HSMCI_WAIT_DATA_RDY()\ + do { \ + cpu_relax(); \ + } while (!(HSMCI_SR & BV(HSMCI_SR_RXRDY))) -#define STROBE_ON() PIOB_SODR = BV(13) -#define STROBE_OFF() PIOB_CODR = BV(13) -#define STROBE_INIT() \ - do { \ - PIOB_OER = BV(13); \ - PIOB_PER = BV(13); \ - } while(0) +#define HSMCI_DMAC_CH 3 -static DECLARE_ISR(hsmci_irq) -{ - kprintf("irq stato %lx\n", HSMCI_SR); -} -void hsmci_readResp(void *resp, size_t len) +void hsmci_readResp(uint32_t *resp, size_t len) { ASSERT(resp); - uint32_t *r = (uint32_t *)resp; - kprintf("size %d %d\n",(len / sizeof(HSMCI_RSPR)), sizeof(HSMCI_RSPR)); - for (size_t i = 0; i < (len / sizeof(HSMCI_RSPR)); i++) - r[i] = HSMCI_RSPR; + for (size_t i = 0; i < len ; i++) + resp[i] = HSMCI_RSPR; } bool hsmci_sendCmd(uint8_t index, uint32_t argument, uint32_t reply_type) { - STROBE_ON(); HSMCI_WAIT(); HSMCI_ARGR = argument; - HSMCI_CMDR = index | reply_type | BV(HSMCI_CMDR_OPDCMD); + HSMCI_CMDR = index | reply_type | BV(HSMCI_CMDR_MAXLAT); uint32_t status; do { status = HSMCI_SR; + if (status & HSMCI_RESP_ERROR_MASK) return status; cpu_relax(); - } while (!(status & (BV(HSMCI_SR_CMDRDY) | BV(HSMCI_SR_NOTBUSY) | BV(HSMCI_SR_XFRDONE)))); - timer_delay(1); - STROBE_OFF(); + } while (!(status & BV(HSMCI_SR_CMDRDY))); + return 0; } +#define HSMCI_WRITE_DMAC_CFG (BV(DMAC_CFG_DST_H2SEL) | \ + BV(DMAC_CFG_SOD) | \ + ((0 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | \ + (0 & DMAC_CFG_SRC_PER_MASK)) + +#define HSMCI_WRITE_DMAC_CTRLB (BV(DMAC_CTRLB_SRC_DSCR) | BV(DMAC_CTRLB_DST_DSCR) | \ + DMAC_CTRLB_FC_MEM2PER_DMA_FC | \ + DMAC_CTRLB_DST_INCR_FIXED | DMAC_CTRLB_SRC_INCR_INCREMENTING) + +#define HSMCI_WRITE_DMAC_CTRLA (DMAC_CTRLA_SRC_WIDTH_WORD | \ + DMAC_CTRLA_DST_WIDTH_WORD) + +#define HSMCI_READ_DMAC_CFG (BV(DMAC_CFG_SRC_H2SEL) | \ + BV(DMAC_CFG_SOD) | \ + ((0 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | \ + (0 & DMAC_CFG_SRC_PER_MASK)) + +#define HSMCI_READ_DMAC_CTRLB (BV(DMAC_CTRLB_SRC_DSCR) | BV(DMAC_CTRLB_DST_DSCR) | \ + DMAC_CTRLB_FC_PER2MEM_DMA_FC | \ + DMAC_CTRLB_DST_INCR_INCREMENTING | DMAC_CTRLB_SRC_INCR_FIXED) + +#define HSMCI_READ_DMAC_CTRLA (DMAC_CTRLA_SRC_WIDTH_WORD | \ + DMAC_CTRLA_DST_WIDTH_WORD) + + +void hsmci_write(const uint32_t *buf, size_t word_num, size_t blk_size) +{ + HSMCI_DMA |= BV(HSMCI_DMA_DMAEN); + HSMCI_BLKR = (blk_size << HSMCI_BLKR_BLKLEN_SHIFT) & ~0x30000; + + dmac_setSources(HSMCI_DMAC_CH, (uint32_t)buf, (uint32_t)&HSMCI_TDR); + dmac_configureDmac(HSMCI_DMAC_CH, word_num, HSMCI_WRITE_DMAC_CFG, HSMCI_WRITE_DMAC_CTRLA, HSMCI_WRITE_DMAC_CTRLB); + dmac_start(HSMCI_DMAC_CH); +} + +void hsmci_read(uint32_t *buf, size_t word_num, size_t blk_size) +{ + HSMCI_DMA |= BV(HSMCI_DMA_DMAEN); + HSMCI_BLKR = blk_size << HSMCI_BLKR_BLKLEN_SHIFT; + + dmac_setSources(HSMCI_DMAC_CH, (uint32_t)&HSMCI_RDR, (uint32_t)buf); + dmac_configureDmac(HSMCI_DMAC_CH, word_num, HSMCI_READ_DMAC_CFG, HSMCI_READ_DMAC_CTRLA, HSMCI_READ_DMAC_CTRLB); + dmac_start(HSMCI_DMAC_CH); +} + + +void hsmci_waitTransfer(void) +{ + while (!(HSMCI_SR & BV(HSMCI_SR_XFRDONE))) + cpu_relax(); +} + +void hsmci_setSpeed(uint32_t data_rate, int flag) +{ + if (flag & HSMCI_HS_MODE) + HSMCI_CFG |= BV(HSMCI_CFG_HSMODE); + else + HSMCI_CFG &= ~BV(HSMCI_CFG_HSMODE); + + HSMCI_MR = HSMCI_CLK_DIV(data_rate); + + timer_delay(10); +} + void hsmci_init(Hsmci *hsmci) { (void)hsmci; - HSMCI_HW_INIT(); - STROBE_INIT(); + SD_PIN_INIT(); pmc_periphEnable(HSMCI_ID); HSMCI_CR = BV(HSMCI_CR_SWRST); @@ -137,11 +179,11 @@ void hsmci_init(Hsmci *hsmci) HSMCI_DTOR = 0xFF | HSMCI_DTOR_DTOMUL_1048576; HSMCI_CSTOR = 0xFF | HSMCI_CSTOR_CSTOMUL_1048576; - HSMCI_MR = HSMCI_CLK_DIV | ((0x7u << HSMCI_MR_PWSDIV_SHIFT) & HSMCI_MR_PWSDIV_MASK); - HSMCI_SDCR = 0; + HSMCI_MR = HSMCI_CLK_DIV(HSMCI_INIT_SPEED); HSMCI_CFG = BV(HSMCI_CFG_FIFOMODE) | BV(HSMCI_CFG_FERRCTRL); - sysirq_setHandler(INT_HSMCI, hsmci_irq); HSMCI_CR = BV(HSMCI_CR_MCIEN); + HSMCI_DMA = 0; + dmac_enableCh(HSMCI_DMAC_CH, NULL); }