X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fcortex-m3%2Fdrv%2Fhsmci_sam3.c;h=b0c0ad0af522693a3afc08a548ee997352e4298d;hb=HEAD;hp=3cd4a4eaac2163a425ff53f54a69161dbc5c6734;hpb=4dc00864c00e6921183e89bb2c4256fef09ff78d;p=bertos.git diff --git a/bertos/cpu/cortex-m3/drv/hsmci_sam3.c b/bertos/cpu/cortex-m3/drv/hsmci_sam3.c index 3cd4a4ea..b0c0ad0a 100644 --- a/bertos/cpu/cortex-m3/drv/hsmci_sam3.c +++ b/bertos/cpu/cortex-m3/drv/hsmci_sam3.c @@ -36,33 +36,27 @@ #include "hsmci_sam3.h" +#include "hw/hw_sd.h" #include -#include #include +#include -#include +#include +#include +#include -#define HSMCI_INIT_SPEED 400000 -#define HSMCI_CLK_DIV ((CPU_FREQ / (HSMCI_INIT_SPEED << 1)) - 1) -#define HSMCI_ERROR_MASK (BV(HSMCI_SR_RINDE) | \ - BV(HSMCI_SR_RDIRE) | \ - BV(HSMCI_SR_RCRCE) | \ - BV(HSMCI_SR_RENDE) | \ - BV(HSMCI_SR_RTOE) | \ - BV(HSMCI_SR_DCRCE) | \ - BV(HSMCI_SR_DTOE) | \ - BV(HSMCI_SR_CSTOE) | \ - BV(HSMCI_SR_BLKOVRE) | \ - BV(HSMCI_SR_ACKRCVE)) +#define HSMCI_CLK_DIV(RATE) ((CPU_FREQ / (RATE << 1)) - 1) #define HSMCI_RESP_ERROR_MASK (BV(HSMCI_SR_RINDE) | BV(HSMCI_SR_RDIRE) \ | BV(HSMCI_SR_RENDE)| BV(HSMCI_SR_RTOE)) +#define HSMCI_DATA_ERROR_MASK (BV(HSMCI_SR_DCRCE) | BV(HSMCI_SR_DTOE)) + #define HSMCI_READY_MASK (BV(HSMCI_SR_CMDRDY) | BV(HSMCI_SR_NOTBUSY)) #define HSMCI_WAIT()\ do { \ @@ -75,101 +69,108 @@ cpu_relax(); \ } while (!(HSMCI_SR & BV(HSMCI_SR_RXRDY))) -#define HSMCI_ERROR() (HSMCI_SR & HSMCI_ERROR_MASK) -#define HSMCI_HW_INIT() \ -do { \ - PIOA_PDR = BV(19) | BV(20) | BV(21) | BV(22) | BV(23) | BV(24); \ - PIO_PERIPH_SEL(PIOA_BASE, BV(19) | BV(20) | BV(21) | BV(22) | BV(23) | BV(24), PIO_PERIPH_A); \ -} while (0) +#define HSMCI_DMAC_CH 3 -#define STROBE_ON() PIOB_SODR = BV(13) -#define STROBE_OFF() PIOB_CODR = BV(13) -#define STROBE_INIT() \ - do { \ - PIOB_OER = BV(13); \ - PIOB_PER = BV(13); \ - } while(0) - -static DECLARE_ISR(hsmci_irq) -{ - if (HSMCI_SR & BV(HSMCI_IER_RTOE)) - { - HSMCI_ARGR = 0; - HSMCI_CMDR = 0 | HSMCI_CMDR_RSPTYP_NORESP | BV(HSMCI_CMDR_OPDCMD); - } -} - -void hsmci_readResp(void *resp, size_t len) +void hsmci_readResp(uint32_t *resp, size_t len) { ASSERT(resp); - uint32_t *r = (uint32_t *)resp; for (size_t i = 0; i < len ; i++) - r[i] = HSMCI_RSPR; + resp[i] = HSMCI_RSPR; } bool hsmci_sendCmd(uint8_t index, uint32_t argument, uint32_t reply_type) { - STROBE_ON(); HSMCI_WAIT(); HSMCI_ARGR = argument; - HSMCI_CMDR = index | reply_type | BV(HSMCI_CMDR_MAXLAT) | BV(HSMCI_CMDR_OPDCMD); + HSMCI_CMDR = index | reply_type | BV(HSMCI_CMDR_MAXLAT); + + uint32_t status; + do { + status = HSMCI_SR; - uint32_t status = HSMCI_SR; - while (!(status & BV(HSMCI_SR_CMDRDY))) - { if (status & HSMCI_RESP_ERROR_MASK) return status; cpu_relax(); - status = HSMCI_SR; - } + } while (!(status & BV(HSMCI_SR_CMDRDY))); - STROBE_OFF(); return 0; } -void hsmci_setBlkSize(size_t blk_size) -{ - HSMCI_DMA = BV(HSMCI_DMA_DMAEN); - HSMCI_BLKR = (blk_size << HSMCI_BLKR_BLKLEN_SHIFT); -} +#define HSMCI_WRITE_DMAC_CFG (BV(DMAC_CFG_DST_H2SEL) | \ + BV(DMAC_CFG_SOD) | \ + ((0 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | \ + (0 & DMAC_CFG_SRC_PER_MASK)) + +#define HSMCI_WRITE_DMAC_CTRLB (BV(DMAC_CTRLB_SRC_DSCR) | BV(DMAC_CTRLB_DST_DSCR) | \ + DMAC_CTRLB_FC_MEM2PER_DMA_FC | \ + DMAC_CTRLB_DST_INCR_FIXED | DMAC_CTRLB_SRC_INCR_INCREMENTING) + +#define HSMCI_WRITE_DMAC_CTRLA (DMAC_CTRLA_SRC_WIDTH_WORD | \ + DMAC_CTRLA_DST_WIDTH_WORD) -bool hsmci_read(uint32_t *buf, size_t word_num) +#define HSMCI_READ_DMAC_CFG (BV(DMAC_CFG_SRC_H2SEL) | \ + BV(DMAC_CFG_SOD) | \ + ((0 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | \ + (0 & DMAC_CFG_SRC_PER_MASK)) + +#define HSMCI_READ_DMAC_CTRLB (BV(DMAC_CTRLB_SRC_DSCR) | BV(DMAC_CTRLB_DST_DSCR) | \ + DMAC_CTRLB_FC_PER2MEM_DMA_FC | \ + DMAC_CTRLB_DST_INCR_INCREMENTING | DMAC_CTRLB_SRC_INCR_FIXED) + +#define HSMCI_READ_DMAC_CTRLA (DMAC_CTRLA_SRC_WIDTH_WORD | \ + DMAC_CTRLA_DST_WIDTH_WORD) + + +void hsmci_write(const uint32_t *buf, size_t word_num, size_t blk_size) { - ASSERT(buf); - ASSERT(!(DMAC_CHSR & BV(DMAC_CHSR_ENA0))); + HSMCI_DMA |= BV(HSMCI_DMA_DMAEN); + HSMCI_BLKR = (blk_size << HSMCI_BLKR_BLKLEN_SHIFT) & ~0x30000; - kprintf("DMAC status %08lx channel st %08lx\n", DMAC_EBCISR, DMAC_CHSR); + dmac_setSources(HSMCI_DMAC_CH, (uint32_t)buf, (uint32_t)&HSMCI_TDR); + dmac_configureDmac(HSMCI_DMAC_CH, word_num, HSMCI_WRITE_DMAC_CFG, HSMCI_WRITE_DMAC_CTRLA, HSMCI_WRITE_DMAC_CTRLB); + dmac_start(HSMCI_DMAC_CH); +} - DMAC_SADDR0 = 0x40000200U; - DMAC_DADDR0 = (uint32_t)buf; - DMAC_DSCR0 = 0; +void hsmci_read(uint32_t *buf, size_t word_num, size_t blk_size) +{ + HSMCI_DMA |= BV(HSMCI_DMA_DMAEN); + HSMCI_BLKR = blk_size << HSMCI_BLKR_BLKLEN_SHIFT; - DMAC_CTRLA0 = word_num | DMAC_CTRLA_SRC_WIDTH_WORD | DMAC_CTRLA_DST_WIDTH_WORD; - DMAC_CTRLB0 = (BV(DMAC_CTRLB_SRC_DSCR) | DMAC_CTRLB_FC_PER2MEM_DMA_FC | - DMAC_CTRLB_SRC_INCR_FIXED | DMAC_CTRLB_DST_INCR_INCREMENTING | BV(DMAC_CTRLB_IEN)); + dmac_setSources(HSMCI_DMAC_CH, (uint32_t)&HSMCI_RDR, (uint32_t)buf); + dmac_configureDmac(HSMCI_DMAC_CH, word_num, HSMCI_READ_DMAC_CFG, HSMCI_READ_DMAC_CTRLA, HSMCI_READ_DMAC_CTRLB); + dmac_start(HSMCI_DMAC_CH); +} - ASSERT(!(DMAC_CHSR & BV(DMAC_CHSR_ENA0))); - DMAC_CHER = BV(DMAC_CHER_ENA0); +void hsmci_waitTransfer(void) +{ while (!(HSMCI_SR & BV(HSMCI_SR_XFRDONE))) cpu_relax(); +} - DMAC_CHDR = BV(DMAC_CHDR_DIS0); - return 0; +void hsmci_setSpeed(uint32_t data_rate, int flag) +{ + if (flag & HSMCI_HS_MODE) + HSMCI_CFG |= BV(HSMCI_CFG_HSMODE); + else + HSMCI_CFG &= ~BV(HSMCI_CFG_HSMODE); + + HSMCI_MR = HSMCI_CLK_DIV(data_rate); + + timer_delay(10); } void hsmci_init(Hsmci *hsmci) { (void)hsmci; - HSMCI_HW_INIT(); - STROBE_INIT(); + SD_PIN_INIT(); pmc_periphEnable(HSMCI_ID); HSMCI_CR = BV(HSMCI_CR_SWRST); @@ -178,23 +179,11 @@ void hsmci_init(Hsmci *hsmci) HSMCI_DTOR = 0xFF | HSMCI_DTOR_DTOMUL_1048576; HSMCI_CSTOR = 0xFF | HSMCI_CSTOR_CSTOMUL_1048576; - HSMCI_MR = HSMCI_CLK_DIV | ((0x7u << HSMCI_MR_PWSDIV_SHIFT) & HSMCI_MR_PWSDIV_MASK) | BV(HSMCI_MR_RDPROOF); - HSMCI_SDCR = 0; + HSMCI_MR = HSMCI_CLK_DIV(HSMCI_INIT_SPEED); HSMCI_CFG = BV(HSMCI_CFG_FIFOMODE) | BV(HSMCI_CFG_FERRCTRL); - sysirq_setHandler(INT_HSMCI, hsmci_irq); HSMCI_CR = BV(HSMCI_CR_MCIEN); - HSMCI_DMA &= ~BV(HSMCI_DMA_DMAEN); - - //init DMAC - DMAC_EBCIDR = 0x3FFFFF; - DMAC_CHDR = BV(DMAC_CHDR_DIS0); - - DMAC_CFG0 = 0; - DMAC_CFG0 = BV(DMAC_CFG_SRC_H2SEL) | DMAC_CFG_FIFOCFG_ALAP_CFG | BV(DMAC_CFG_SOD); - - pmc_periphEnable(DMAC_ID); - DMAC_EN = BV(DMAC_EN_ENABLE); + HSMCI_DMA = 0; - //HSMCI_IER = BV(HSMCI_IER_RTOE); + dmac_enableCh(HSMCI_DMAC_CH, NULL); }