X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fcortex-m3%2Fdrv%2Fhsmci_sam3.c;h=cfc1c8b6eb4677815ec39bb2f8d797647c435d05;hb=4ddace69429f1b24dfccfba49d2e47ae059609d3;hp=13b2f1367940f033cde1202e68edc28a86b41c22;hpb=8a6460473f0a31c528617ffde51aa88985725c7a;p=bertos.git diff --git a/bertos/cpu/cortex-m3/drv/hsmci_sam3.c b/bertos/cpu/cortex-m3/drv/hsmci_sam3.c index 13b2f136..cfc1c8b6 100644 --- a/bertos/cpu/cortex-m3/drv/hsmci_sam3.c +++ b/bertos/cpu/cortex-m3/drv/hsmci_sam3.c @@ -43,10 +43,20 @@ #include +/** DMA Transfer Descriptor as well as Linked List Item */ +typedef struct DmacDesc +{ + uint32_t src_addr; /**< Source buffer address */ + uint32_t dst_addr; /**< Destination buffer address */ + uint32_t ctrl_a; /**< Control A register settings */ + uint32_t ctrl_b; /**< Control B register settings */ + uint32_t dsc_addr; /**< Next descriptor address */ +} DmacDesc; + + -#define HSMCI_INIT_SPEED 400000 -#define HSMCI_CLK_DIV ((CPU_FREQ / (HSMCI_INIT_SPEED << 1)) - 1) +#define HSMCI_CLK_DIV(RATE) ((CPU_FREQ / (RATE << 1)) - 1) #define HSMCI_ERROR_MASK (BV(HSMCI_SR_RINDE) | \ BV(HSMCI_SR_RDIRE) | \ @@ -61,13 +71,21 @@ #define HSMCI_RESP_ERROR_MASK (BV(HSMCI_SR_RINDE) | BV(HSMCI_SR_RDIRE) \ - | BV(HSMCI_SR_RCRCE)| BV(HSMCI_SR_RENDE)| BV(HSMCI_SR_RTOE)) + | BV(HSMCI_SR_RENDE)| BV(HSMCI_SR_RTOE)) +#define HSMCI_DATA_ERROR_MASK (BV(HSMCI_SR_DCRCE) | BV(HSMCI_SR_DTOE)) +#define HSMCI_READY_MASK (BV(HSMCI_SR_CMDRDY) | BV(HSMCI_SR_NOTBUSY)) #define HSMCI_WAIT()\ do { \ cpu_relax(); \ - } while (!(HSMCI_SR & (BV(HSMCI_SR_CMDRDY) | BV(HSMCI_SR_NOTBUSY) | BV(HSMCI_SR_XFRDONE)))) + } while (!(HSMCI_SR & BV(HSMCI_SR_CMDRDY))) + + +#define HSMCI_WAIT_DATA_RDY()\ + do { \ + cpu_relax(); \ + } while (!(HSMCI_SR & BV(HSMCI_SR_RXRDY))) #define HSMCI_ERROR() (HSMCI_SR & HSMCI_ERROR_MASK) @@ -88,17 +106,29 @@ do { \ static DECLARE_ISR(hsmci_irq) { - kprintf("irq stato %lx\n", HSMCI_SR); + uint32_t status = HSMCI_SR; + if (status & BV(HSMCI_IER_DMADONE)) + { + } +} + + +static DECLARE_ISR(dmac_irq) +{ + uint32_t stat = DMAC_EBCISR; + + if (stat & BV(DMAC_EBCISR_ERR3)) + { + kprintf("err %08lx\n", stat); + } } -void hsmci_readResp(void *resp, size_t len) +void hsmci_readResp(uint32_t *resp, size_t len) { ASSERT(resp); - uint32_t *r = (uint32_t *)resp; - kprintf("size %d %d\n",(len / sizeof(HSMCI_RSPR)), sizeof(HSMCI_RSPR)); - for (size_t i = 0; i < (len / sizeof(HSMCI_RSPR)); i++) - r[i] = HSMCI_RSPR; + for (size_t i = 0; i < len ; i++) + resp[i] = HSMCI_RSPR; } bool hsmci_sendCmd(uint8_t index, uint32_t argument, uint32_t reply_type) @@ -107,22 +137,90 @@ bool hsmci_sendCmd(uint8_t index, uint32_t argument, uint32_t reply_type) HSMCI_WAIT(); HSMCI_ARGR = argument; - HSMCI_CMDR = index | reply_type | BV(HSMCI_CMDR_OPDCMD); + HSMCI_CMDR = index | reply_type | BV(HSMCI_CMDR_MAXLAT); - uint32_t status; - do { - status = HSMCI_SR; + uint32_t status = HSMCI_SR; + while (!(status & BV(HSMCI_SR_CMDRDY))) + { if (status & HSMCI_RESP_ERROR_MASK) return status; cpu_relax(); - } while (!(status & (BV(HSMCI_SR_CMDRDY) | BV(HSMCI_SR_NOTBUSY) | BV(HSMCI_SR_XFRDONE)))); - timer_delay(1); + status = HSMCI_SR; + } + STROBE_OFF(); return 0; } +INLINE void hsmci_setBlockSize(size_t blk_size) +{ + HSMCI_DMA |= BV(HSMCI_DMA_DMAEN); + HSMCI_BLKR = blk_size << HSMCI_BLKR_BLKLEN_SHIFT; +} + +void hsmci_prgTxDMA(const uint32_t *buf, size_t word_num, size_t blk_size) +{ + + hsmci_setBlockSize(blk_size); + + DMAC_CHDR = BV(DMAC_CHDR_DIS0); + + DMAC_SADDR0 = (uint32_t)buf; + DMAC_DADDR0 = (uint32_t)&HSMCI_TDR; + DMAC_DSCR0 = 0; + + DMAC_CFG0 = BV(DMAC_CFG_DST_H2SEL) | DMAC_CFG_FIFOCFG_ALAP_CFG | (0x1 << DMAC_CFG_AHB_PROT_SHIFT); + DMAC_CTRLA0 = (word_num & DMAC_CTRLA_BTSIZE_MASK) | + DMAC_CTRLA_SRC_WIDTH_WORD | DMAC_CTRLA_DST_WIDTH_WORD; + DMAC_CTRLB0 = (BV(DMAC_CTRLB_SRC_DSCR) | BV(DMAC_CTRLB_DST_DSCR) | DMAC_CTRLB_FC_MEM2PER_DMA_FC | + DMAC_CTRLB_DST_INCR_FIXED | DMAC_CTRLB_SRC_INCR_INCREMENTING | BV(DMAC_CTRLB_IEN)); + + ASSERT(!(DMAC_CHSR & BV(DMAC_CHSR_ENA0))); + DMAC_CHER = BV(DMAC_CHER_ENA0); + +} + +void hsmci_prgRxDMA(uint32_t *buf, size_t word_num, size_t blk_size) +{ + hsmci_setBlockSize(blk_size); + + DMAC_CHDR = BV(DMAC_CHDR_DIS0); + + DMAC_SADDR0 = (uint32_t)&HSMCI_RDR; + DMAC_DADDR0 = (uint32_t)buf; + DMAC_DSCR0 = 0; + + DMAC_CFG0 = BV(DMAC_CFG_SRC_H2SEL) | DMAC_CFG_FIFOCFG_ALAP_CFG | (0x1 << DMAC_CFG_AHB_PROT_SHIFT); + DMAC_CTRLA0 = (word_num & DMAC_CTRLA_BTSIZE_MASK) | + DMAC_CTRLA_SRC_WIDTH_WORD | DMAC_CTRLA_DST_WIDTH_WORD; + DMAC_CTRLB0 = (BV(DMAC_CTRLB_SRC_DSCR) | BV(DMAC_CTRLB_DST_DSCR) | DMAC_CTRLB_FC_PER2MEM_DMA_FC | + DMAC_CTRLB_DST_INCR_INCREMENTING | DMAC_CTRLB_SRC_INCR_FIXED | BV(DMAC_CTRLB_IEN)); + + ASSERT(!(DMAC_CHSR & BV(DMAC_CHSR_ENA0))); + DMAC_CHER = BV(DMAC_CHER_ENA0); +} + + +void hsmci_waitTransfer(void) +{ + while (!(HSMCI_SR & BV(HSMCI_SR_XFRDONE))) + cpu_relax(); +} + +void hsmci_setSpeed(uint32_t data_rate, int flag) +{ + if (flag) + HSMCI_CFG |= BV(HSMCI_CFG_HSMODE); + else + HSMCI_CFG &= ~BV(HSMCI_CFG_HSMODE); + + HSMCI_MR = HSMCI_CLK_DIV(data_rate) | ((0x7u << HSMCI_MR_PWSDIV_SHIFT) & HSMCI_MR_PWSDIV_MASK); + + timer_delay(10); +} + void hsmci_init(Hsmci *hsmci) { (void)hsmci; @@ -137,11 +235,21 @@ void hsmci_init(Hsmci *hsmci) HSMCI_DTOR = 0xFF | HSMCI_DTOR_DTOMUL_1048576; HSMCI_CSTOR = 0xFF | HSMCI_CSTOR_CSTOMUL_1048576; - HSMCI_MR = HSMCI_CLK_DIV | ((0x7u << HSMCI_MR_PWSDIV_SHIFT) & HSMCI_MR_PWSDIV_MASK); - HSMCI_SDCR = 0; + HSMCI_MR = HSMCI_CLK_DIV(HSMCI_INIT_SPEED) | ((0x7u << HSMCI_MR_PWSDIV_SHIFT) & HSMCI_MR_PWSDIV_MASK) | BV(HSMCI_MR_RDPROOF); HSMCI_CFG = BV(HSMCI_CFG_FIFOMODE) | BV(HSMCI_CFG_FERRCTRL); sysirq_setHandler(INT_HSMCI, hsmci_irq); HSMCI_CR = BV(HSMCI_CR_MCIEN); + HSMCI_DMA = 0; + + //init DMAC + DMAC_EBCIDR = 0x3FFFFF; + DMAC_CHDR = 0x1F; + + + pmc_periphEnable(DMAC_ID); + DMAC_EN = BV(DMAC_EN_ENABLE); + sysirq_setHandler(INT_DMAC, dmac_irq); + DMAC_EBCIER = BV(DMAC_EBCIER_BTC0) | BV(DMAC_EBCIER_ERR0); }