X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fcortex-m3%2Fdrv%2Fi2c_lm3s.c;h=fd2f5905d4abe74a1ab802feda478b0806f35012;hb=8016ea0a758a96d75ee7d64c773990b38d94fa8e;hp=27fed7c69e06985e5a51a29661332baa07b4a186;hpb=544c3f3025ae00b1500d94e5b616270601a0efc7;p=bertos.git diff --git a/bertos/cpu/cortex-m3/drv/i2c_lm3s.c b/bertos/cpu/cortex-m3/drv/i2c_lm3s.c index 27fed7c6..fd2f5905 100644 --- a/bertos/cpu/cortex-m3/drv/i2c_lm3s.c +++ b/bertos/cpu/cortex-m3/drv/i2c_lm3s.c @@ -32,6 +32,8 @@ * * \brief Driver for the LM3S I2C (implementation) * + * \author Daniele Basile + * */ #include "cfg/cfg_i2c.h" @@ -43,123 +45,212 @@ #include #include // BV() -#include #include #include +#include +#include + +#include + #include #include +#include +#include -/** - * Send START condition on the bus. - * - * \return true on success, false otherwise. - */ -static bool i2c_builtin_start(void) +struct I2cHardware { + uint32_t base; + uint32_t sys_cntl; + uint32_t sys_gpio; + uint32_t pin_mask; + uint32_t gpio_base; + bool first_xtranf; +}; - return false; -} +#define WAIT_BUSY(base) \ + do { \ + while (HWREG(base + I2C_O_MCS) & I2C_MCS_BUSY ) \ + cpu_relax(); \ + } while (0); -/** - * Send START condition and select slave for write. - * \c id is the device id comprehensive of address left shifted by 1. - * The LSB of \c id is ignored and reset to 0 for write operation. - * - * \return true on success, false otherwise. +/* + * The start is not performed when we call the start function + * because the hardware should know the first data byte to send. + * Generally to perform a byte send we should write the slave address + * in slave address register and the first byte to send in data registry. + * After then we can perform the start write procedure, and send really + * the our data. To use common bertos i2c api the really start will be + * performed when the user "put" or "send" its data. These tricks are hide + * from the driver implementation. */ -bool i2c_builtin_start_w(uint8_t id) +static void i2c_lm3s_start(struct I2c *i2c, uint16_t slave_addr) { - /* - * Loop on the select write sequence: when the eeprom is busy - * writing previously sent data it will reply to the SLA_W - * control byte with a NACK. In this case, we must - * keep trying until the eeprom responds with an ACK. - */ - ticks_t start = timer_clock(); - while (i2c_builtin_start()) - { - else if (timer_clock() - start > ms_to_ticks(CONFIG_I2C_START_TIMEOUT)) - { - LOG_ERR("Timeout on TWI_MT_START\n"); - break; - } - } + i2c->hw->first_xtranf = true; - return false; + if (I2C_TEST_START(i2c->flags) == I2C_START_W) + HWREG(i2c->hw->base + I2C_O_MSA) = slave_addr & ~BV(0); + else /* (I2C_TEST_START(i2c->flags) == I2C_START_R) */ + HWREG(i2c->hw->base + I2C_O_MSA) = slave_addr | BV(0); } - -/** - * Send START condition and select slave for read. - * \c id is the device id comprehensive of address left shifted by 1. - * The LSB of \c id is ignored and set to 1 for read operation. - * - * \return true on success, false otherwise. - */ -bool i2c_builtin_start_r(uint8_t id) +INLINE bool wait_addrAck(I2c *i2c, uint32_t mode_mask) { - if (i2c_builtin_start()) + ticks_t start = timer_clock(); + while (1) { + uint32_t status = HWREG(i2c->hw->base + I2C_O_MCS); - } + if (timer_clock() - start > ms_to_ticks(CONFIG_I2C_START_TIMEOUT)) + return false; - return false; -} + if(status & I2C_MCS_ADRACK) + { + HWREG(i2c->hw->base + I2C_O_MCS) = mode_mask; + WAIT_BUSY(i2c->hw->base); + } + else + break; + cpu_relax(); + } + return true; +} -/** - * Send STOP condition. - */ -void i2c_builtin_stop(void) +static void i2c_lm3s_putc(I2c *i2c, const uint8_t data) { + HWREG(i2c->hw->base + I2C_O_MDR) = data; -} + if (i2c->hw->first_xtranf) + { + HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_RUN | I2C_MCS_START; + while( HWREG(i2c->hw->base + I2C_O_MCS) & I2C_MCS_BUSY ); + if (!wait_addrAck(i2c, I2C_MCS_RUN | I2C_MCS_START)) + { + LOG_ERR("Start timeout\n"); + i2c->errors |= I2C_START_TIMEOUT; + HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_STOP; + WAIT_BUSY(i2c->hw->base); + return; + } -/** - * Put a single byte in master transmitter mode - * to the selected slave device through the TWI bus. - * - * \return true on success, false on error. - */ -bool i2c_builtin_put(const uint8_t data) -{ - return true; + i2c->hw->first_xtranf = false; + } + else + { + HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_RUN; + WAIT_BUSY(i2c->hw->base); + } + + if ((i2c->xfer_size == 1) && (I2C_TEST_STOP(i2c->flags) == I2C_STOP)) + { + HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_STOP; + WAIT_BUSY(i2c->hw->base); + } } -/** - * Get 1 byte from slave in master transmitter mode - * to the selected slave device through the I2C bus. - * If \a ack is true issue a ACK after getting the byte, - * otherwise a NACK is issued. - * - * \return the byte read if ok, EOF on errors. - */ -int i2c_builtin_get(bool ack) +static uint8_t i2c_lm3s_getc(I2c *i2c) { - - if (ack) + uint8_t data; + if (i2c->hw->first_xtranf) { + uint32_t start_mode; + if (i2c->xfer_size == 1) + start_mode = I2C_MCS_RUN | I2C_MCS_START; + else + start_mode = I2C_MCS_ACK | I2C_MCS_RUN | I2C_MCS_START; + + HWREG(i2c->hw->base + I2C_O_MCS) = start_mode; + WAIT_BUSY(i2c->hw->base); + if (!wait_addrAck(i2c, start_mode)) + { + LOG_ERR("Start timeout\n"); + i2c->errors |= I2C_START_TIMEOUT; + HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_STOP; + WAIT_BUSY(i2c->hw->base); + return 0xFF; + } + data = HWREG(i2c->hw->base + I2C_O_MDR); + i2c->hw->first_xtranf = false; } else { + if (i2c->xfer_size > 1) + HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_ACK | I2C_MCS_RUN; + else + HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_RUN; + WAIT_BUSY(i2c->hw->base); + data = HWREG(i2c->hw->base + I2C_O_MDR); } - /* avoid sign extension */ - return 0; + if ((i2c->xfer_size == 1) && (I2C_TEST_STOP(i2c->flags) == I2C_STOP)) + { + HWREG(i2c->hw->base + I2C_O_MCS) = I2C_MCS_STOP; + WAIT_BUSY(i2c->hw->base); + } + return data; } -MOD_DEFINE(i2c); +static const I2cVT i2c_lm3s_vt = +{ + .start = i2c_lm3s_start, + .getc = i2c_lm3s_getc, + .putc = i2c_lm3s_putc, + .write = i2c_genericWrite, + .read = i2c_genericRead, +}; + +static struct I2cHardware i2c_lm3s_hw[] = +{ + { /* I2C0 */ + .base = I2C0_MASTER_BASE, + .sys_cntl = SYSCTL_RCGC1_I2C0, + .sys_gpio = SYSCTL_RCGC2_GPIOB, + .pin_mask = (GPIO_I2C0_SCL_PIN | GPIO_I2C0_SDA_PIN), + .gpio_base = GPIO_PORTB_BASE, + }, + { /* I2C1 */ + .base = I2C1_MASTER_BASE, + .sys_cntl = SYSCTL_RCGC1_I2C1, + .sys_gpio = SYSCTL_RCGC2_GPIOA, + .pin_mask = (GPIO_I2C1_SCL_PIN | GPIO_I2C1_SDA_PIN), + .gpio_base = GPIO_PORTA_BASE, + }, +}; /** * Initialize I2C module. */ -void i2c_builtin_init(void) +void i2c_hw_init(I2c *i2c, int dev, uint32_t clock) { - MOD_INIT(i2c); + i2c->hw = &i2c_lm3s_hw[dev]; + i2c->vt = &i2c_lm3s_vt; + + /* Enable the peripheral clock */ + SYSCTL_RCGC1_R |= i2c->hw->sys_cntl; + SYSCTL_RCGC2_R |= i2c->hw->sys_gpio; + + /* Configure GPIO pins to work as I2C pins */ + lm3s_gpioPinConfig(i2c->hw->gpio_base, i2c->hw->pin_mask, + GPIO_DIR_MODE_HW, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD_WPU); + /* + * Note: to set correctly the i2c speed we shold before enable the i2c + * device and then set in master time period the correct value + */ + + /* Enable i2c device */ + HWREG(i2c->hw->base + I2C_O_MCR) |= I2C_MCR_MFE; + + /* + * Compute the clock divider that achieves the fastest speed less than or + * equal to the desired speed. The numerator is biased to favor a larger + * clock divider so that the resulting clock is always less than or equal + * to the desired clock, never greater. + */ + HWREG(i2c->hw->base + I2C_O_MTPR) = ((CPU_FREQ + (2 * 10 * clock) - 1) / (2 * 10 * clock)) - 1; }