X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fcortex-m3%2Fdrv%2Fi2s_sam3.c;h=0b8b6988f75e6a131ce2ae83db8976dad7b06029;hb=fe1e84aff4fe0924a8e51a1792e5731ae0ea3b52;hp=cb8c61d7566821ca033373c12ede7f6ecca8e441;hpb=82f41e5602dce5e8b7a3a8c2872c2091c79eefe2;p=bertos.git diff --git a/bertos/cpu/cortex-m3/drv/i2s_sam3.c b/bertos/cpu/cortex-m3/drv/i2s_sam3.c index cb8c61d7..0b8b6988 100644 --- a/bertos/cpu/cortex-m3/drv/i2s_sam3.c +++ b/bertos/cpu/cortex-m3/drv/i2s_sam3.c @@ -59,16 +59,41 @@ #define I2S_DMAC_CH 3 - #define I2S_CACHED_CHUNK_SIZE 2 + #define I2S_TX_DMAC_CFG (BV(DMAC_CFG_DST_H2SEL) | \ BV(DMAC_CFG_SOD) | \ ((3 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | \ (4 & DMAC_CFG_SRC_PER_MASK)) -#define I2S_TX_DMAC_CTRLA (DMAC_CTRLA_SRC_WIDTH_HALF_WORD | \ + +#if CONFIG_WORD_BIT_SIZE == 32 + #define I2S_TX_DMAC_CTRLA (DMAC_CTRLA_SRC_WIDTH_WORD | \ + DMAC_CTRLA_DST_WIDTH_WORD) + #define I2S_RX_DMAC_CTRLA (DMAC_CTRLA_SRC_WIDTH_WORD | \ + DMAC_CTRLA_DST_WIDTH_WORD) + #define I2S_WORD_BYTE_SIZE 4 +#elif CONFIG_WORD_BIT_SIZE == 16 + + #define I2S_TX_DMAC_CTRLA (DMAC_CTRLA_SRC_WIDTH_HALF_WORD | \ + DMAC_CTRLA_DST_WIDTH_HALF_WORD) + #define I2S_RX_DMAC_CTRLA (DMAC_CTRLA_SRC_WIDTH_HALF_WORD | \ + DMAC_CTRLA_DST_WIDTH_HALF_WORD) + #define I2S_WORD_BYTE_SIZE 2 + +#elif CONFIG_WORD_BIT_SIZE == 8 + + #define I2S_TX_DMAC_CTRLA (DMAC_CTRLA_SRC_WIDTH_BYTE | \ + DMAC_CTRLA_DST_WIDTH_BYTE) + #define I2S_RX_DMAC_CTRLA (DMAC_CTRLA_SRC_WIDTH_BYTE | \ DMAC_CTRLA_DST_WIDTH_HALF_WORD) + #define I2S_WORD_BYTE_SIZE 1 + +#else + #error Wrong i2s word size. +#endif + #define I2S_TX_DMAC_CTRLB (DMAC_CTRLB_FC_MEM2PER_DMA_FC | \ DMAC_CTRLB_DST_INCR_FIXED | \ @@ -76,17 +101,19 @@ #define I2S_RX_DMAC_CFG (BV(DMAC_CFG_SRC_H2SEL) | \ BV(DMAC_CFG_SOD) | \ - ((3 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | \ + ((4 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | \ (4 & DMAC_CFG_SRC_PER_MASK)) -#define I2S_RX_DMAC_CTRLA (DMAC_CTRLA_SRC_WIDTH_HALF_WORD | \ - DMAC_CTRLA_DST_WIDTH_HALF_WORD) - #define I2S_RX_DMAC_CTRLB (DMAC_CTRLB_FC_PER2MEM_DMA_FC | \ DMAC_CTRLB_DST_INCR_INCREMENTING | \ DMAC_CTRLB_SRC_INCR_FIXED) + +#define I2S_STATUS_ERR BV(0) +#define I2S_STATUS_SINGLE_TRASF BV(1) +#define I2S_STATUS_TX BV(2) +#define I2S_STATUS_RX BV(3) struct I2sHardware { bool end; @@ -101,15 +128,13 @@ DmacDesc *curr; DmacDesc *next; DmacDesc *prev; -bool error = false; -static int16_t *sample_buff; +static uint8_t i2s_status; +static uint8_t *sample_buff; static size_t next_idx = 0; static size_t chunk_size = 0; static size_t remaing_size = 0; static size_t transfer_size = 0; -static bool single_transfer; - static void sam3_i2s_txStop(I2s *i2s) { (void)i2s; @@ -121,6 +146,8 @@ static void sam3_i2s_txStop(I2s *i2s) next_idx = 0; transfer_size = 0; + i2s_status &= ~I2S_STATUS_TX; + event_do(&data_ready); } @@ -133,15 +160,15 @@ static void sam3_i2s_txWait(I2s *i2s) static void i2s_dmac_irq(uint32_t status) { I2S_STROBE_ON(); - if (single_transfer) + if (i2s_status & I2S_STATUS_SINGLE_TRASF) { - single_transfer = false; + i2s_status &= ~I2S_STATUS_SINGLE_TRASF; } else { if (status & (BV(I2S_DMAC_CH) << DMAC_EBCIDR_ERR0)) { - error = true; + i2s_status |= I2S_STATUS_ERR; // Disable to reset channel and clear fifo dmac_stop(I2S_DMAC_CH); } @@ -151,11 +178,22 @@ static void i2s_dmac_irq(uint32_t status) curr = next; next = prev; - curr->src_addr = (uint32_t)&sample_buff[next_idx]; - curr->dst_addr = (uint32_t)&SSC_THR; - curr->dsc_addr = (uint32_t)next; - curr->ctrla = I2S_TX_DMAC_CTRLA | (chunk_size & 0xffff); - curr->ctrlb = I2S_TX_DMAC_CTRLB & ~BV(DMAC_CTRLB_IEN); + if (i2s_status & I2S_STATUS_TX) + { + curr->src_addr = (uint32_t)&sample_buff[next_idx]; + curr->dst_addr = (uint32_t)&SSC_THR; + curr->dsc_addr = (uint32_t)next; + curr->ctrla = I2S_TX_DMAC_CTRLA | ((chunk_size / I2S_WORD_BYTE_SIZE) & 0xffff); + curr->ctrlb = I2S_TX_DMAC_CTRLB & ~BV(DMAC_CTRLB_IEN); + } + else + { + curr->src_addr = (uint32_t)&SSC_RHR; + curr->dst_addr = (uint32_t)&sample_buff[next_idx]; + curr->dsc_addr = (uint32_t)next; + curr->ctrla = I2S_RX_DMAC_CTRLA | ((chunk_size / I2S_WORD_BYTE_SIZE) & 0xffff); + curr->ctrlb = I2S_RX_DMAC_CTRLB & ~BV(DMAC_CTRLB_IEN); + } remaing_size -= chunk_size; next_idx += chunk_size; @@ -179,13 +217,13 @@ static void sam3_i2s_txStart(I2s *i2s, void *buf, size_t len, size_t slice_len) ASSERT(!(len % slice_len)); i2s->hw->end = false; - single_transfer = false; + i2s_status &= ~I2S_STATUS_SINGLE_TRASF; - sample_buff = (int16_t *)buf; + sample_buff = (uint8_t *)buf; next_idx = 0; - chunk_size = slice_len / 2; - remaing_size = len / 2; - transfer_size = len / 2; + chunk_size = slice_len; + remaing_size = len; + transfer_size = len; memset(&lli0, 0, sizeof(DmacDesc)); @@ -201,12 +239,12 @@ static void sam3_i2s_txStart(I2s *i2s, void *buf, size_t len, size_t slice_len) curr = next; next = prev; - i2s->ctx.tx_callback(i2s, &sample_buff[next_idx], chunk_size * 2); + i2s->ctx.tx_callback(i2s, &sample_buff[next_idx], chunk_size); curr->src_addr = (uint32_t)&sample_buff[next_idx]; curr->dst_addr = (uint32_t)&SSC_THR; curr->dsc_addr = (uint32_t)next; - curr->ctrla = I2S_TX_DMAC_CTRLA | (chunk_size & 0xffff); + curr->ctrla = I2S_TX_DMAC_CTRLA | ((chunk_size / I2S_WORD_BYTE_SIZE) & 0xffff); curr->ctrlb = I2S_TX_DMAC_CTRLB & ~BV(DMAC_CTRLB_IEN); remaing_size -= chunk_size; @@ -225,14 +263,16 @@ static void sam3_i2s_txStart(I2s *i2s, void *buf, size_t len, size_t slice_len) return; } - error = false; + i2s_status &= ~I2S_STATUS_ERR; + i2s_status |= I2S_STATUS_TX; + SSC_CR = BV(SSC_TXEN); I2S_STROBE_OFF(); while (1) { event_wait(&data_ready); - if (error) + if (i2s_status & I2S_STATUS_ERR) { LOG_ERR("Error while streaming.\n"); break; @@ -244,7 +284,7 @@ static void sam3_i2s_txStart(I2s *i2s, void *buf, size_t len, size_t slice_len) break; } - i2s->ctx.tx_callback(i2s, &sample_buff[next_idx], chunk_size * 2); + i2s->ctx.tx_callback(i2s, &sample_buff[next_idx], chunk_size); cpu_relax(); } } @@ -252,20 +292,98 @@ static void sam3_i2s_txStart(I2s *i2s, void *buf, size_t len, size_t slice_len) static void sam3_i2s_rxStop(I2s *i2s) { (void)i2s; - SSC_CR = BV(SSC_TXDIS); + SSC_CR = BV(SSC_RXDIS) | BV(SSC_TXDIS); + dmac_stop(I2S_DMAC_CH); + + i2s->hw->end = true; + remaing_size = 0; + next_idx = 0; + transfer_size = 0; + + i2s_status &= ~I2S_STATUS_RX; + + event_do(&data_ready); } static void sam3_i2s_rxWait(I2s *i2s) { (void)i2s; + event_wait(&data_ready); } static void sam3_i2s_rxStart(I2s *i2s, void *buf, size_t len, size_t slice_len) { - (void)i2s; - (void)buf; - (void)len; - (void)slice_len; + ASSERT(buf); + ASSERT(len >= slice_len); + ASSERT(!(len % slice_len)); + + i2s->hw->end = false; + i2s_status &= ~I2S_STATUS_SINGLE_TRASF; + + sample_buff = (uint8_t *)buf; + next_idx = 0; + chunk_size = slice_len; + remaing_size = len; + transfer_size = len; + + memset(&lli0, 0, sizeof(DmacDesc)); + memset(&lli1, 0, sizeof(DmacDesc)); + + prev = 0; + curr = &lli1; + next = &lli0; + + for (int i = 0; i < I2S_CACHED_CHUNK_SIZE; i++) + { + prev = curr; + curr = next; + next = prev; + + i2s->ctx.rx_callback(i2s, &sample_buff[next_idx], chunk_size); + curr->src_addr = (uint32_t)&SSC_RHR; + curr->dst_addr = (uint32_t)&sample_buff[next_idx]; + curr->dsc_addr = (uint32_t)next; + curr->ctrla = I2S_RX_DMAC_CTRLA | ((chunk_size / I2S_WORD_BYTE_SIZE) & 0xffff); + curr->ctrlb = I2S_RX_DMAC_CTRLB & ~BV(DMAC_CTRLB_IEN); + + remaing_size -= chunk_size; + next_idx += chunk_size; + + if (chunk_size > remaing_size) + break; + + } + dmac_setLLITransfer(I2S_DMAC_CH, prev, I2S_RX_DMAC_CFG); + + if (dmac_start(I2S_DMAC_CH) < 0) + { + LOG_ERR("DMAC start[%x]\n", dmac_error(I2S_DMAC_CH)); + return; + } + + i2s_status &= ~I2S_STATUS_ERR; + i2s_status |= I2S_STATUS_RX; + + SSC_CR = BV(SSC_RXEN) | BV(SSC_TXEN); + I2S_STROBE_OFF(); + + while (1) + { + event_wait(&data_ready); + if (i2s_status & I2S_STATUS_ERR) + { + LOG_ERR("Error while streaming.\n"); + break; + } + + if (i2s->hw->end) + { + LOG_INFO("Stop streaming.\n"); + break; + } + i2s->ctx.rx_callback(i2s, &sample_buff[next_idx], chunk_size); + cpu_relax(); + } } @@ -282,11 +400,10 @@ static bool sam3_i2s_isRxFinish(struct I2s *i2s) static void sam3_i2s_txBuf(struct I2s *i2s, void *buf, size_t len) { (void)i2s; - - single_transfer = true; + i2s_status |= I2S_STATUS_SINGLE_TRASF; dmac_setSources(I2S_DMAC_CH, (uint32_t)buf, (uint32_t)&SSC_THR); - dmac_configureDmac(I2S_DMAC_CH, len, I2S_TX_DMAC_CFG, I2S_TX_DMAC_CTRLA, I2S_TX_DMAC_CTRLB); + dmac_configureDmac(I2S_DMAC_CH, len / I2S_WORD_BYTE_SIZE, I2S_TX_DMAC_CFG, I2S_TX_DMAC_CTRLA, I2S_TX_DMAC_CTRLB); dmac_start(I2S_DMAC_CH); SSC_CR = BV(SSC_TXEN); @@ -296,10 +413,10 @@ static void sam3_i2s_rxBuf(struct I2s *i2s, void *buf, size_t len) { (void)i2s; - single_transfer = true; + i2s_status |= I2S_STATUS_SINGLE_TRASF; dmac_setSources(I2S_DMAC_CH, (uint32_t)&SSC_RHR, (uint32_t)buf); - dmac_configureDmac(I2S_DMAC_CH, len, I2S_RX_DMAC_CFG, I2S_RX_DMAC_CTRLA, I2S_RX_DMAC_CTRLB); + dmac_configureDmac(I2S_DMAC_CH, len / I2S_WORD_BYTE_SIZE, I2S_RX_DMAC_CFG, I2S_RX_DMAC_CTRLA, I2S_RX_DMAC_CTRLB); dmac_start(I2S_DMAC_CH); SSC_CR = BV(SSC_RXEN); @@ -362,6 +479,7 @@ void i2s_init(I2s *i2s, int channel) PIOA_PDR = BV(SSC_TK) | BV(SSC_TF) | BV(SSC_TD); PIO_PERIPH_SEL(PIOA_BASE, BV(SSC_TK) | BV(SSC_TF) | BV(SSC_TD), PIO_PERIPH_B); + PIOB_PDR = BV(SSC_RD) | BV(SSC_RF); PIO_PERIPH_SEL(PIOB_BASE, BV(SSC_RD) | BV(SSC_RF), PIO_PERIPH_A);