X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fcortex-m3%2Fdrv%2Fi2s_sam3.c;h=526a08b9badfbaf648fd38e674c6fa272d90bab7;hb=666af47976ef74df740dc7df58fc31fa6e3fc65b;hp=8a35c58166d7f9c38c15d7a30dd87bba88cc46b7;hpb=d828b90743ba303ae954220ffa968990dfff5963;p=bertos.git diff --git a/bertos/cpu/cortex-m3/drv/i2s_sam3.c b/bertos/cpu/cortex-m3/drv/i2s_sam3.c index 8a35c581..526a08b9 100644 --- a/bertos/cpu/cortex-m3/drv/i2s_sam3.c +++ b/bertos/cpu/cortex-m3/drv/i2s_sam3.c @@ -35,11 +35,6 @@ */ -/* - * TODO: Revise the public api of this module to be more generic. Evalutate to - * implement the more generic layer to be common to all I2S BeRTOS drivers. - */ -#include "i2s_sam3.h" #include "cfg/cfg_i2s.h" // Define log settings for cfg/log.h. @@ -48,135 +43,145 @@ #include #include -#include - +#include #include #include -#define DATALEN (15 & SSC_DATLEN_MASK) -// FIXME: this is not correct for 16 <= DATALEN < 24 -#define PDC_DIV ((DATALEN / 8) + 1) -/* - * PDC_DIV must be 1, 2 or 4, which are the bytes that are transferred - * each time the PDC reads from memory. - */ -STATIC_ASSERT(PDC_DIV % 2 == 0); -#define PDC_COUNT (CONFIG_PLAY_BUF_LEN / PDC_DIV) +struct I2sHardware +{ +}; + +struct I2sHardware i2s_hw; + + +/* We divite for 2 because the min clock for i2s i MCLK/2 */ +#define MCK_DIV (CPU_FREQ / (48000 * CONFIG_WORD_BIT_SIZE * CONFIG_CHANNEL_NUM * 2)) +#define DATALEN ((CONFIG_WORD_BIT_SIZE - 1) & SSC_DATLEN_MASK) +#define DELAY ((CONFIG_DELAY << SSC_STTDLY_SHIFT) & SSC_STTDLY_MASK) +#define PERIOD ((CONFIG_PERIOD << (SSC_PERIOD_SHIFT)) & SSC_PERIOD_MASK) +#define DATNB ((CONFIG_WORD_PER_FRAME << SSC_DATNB_SHIFT) & SSC_DATNB_MASK) +#define FSLEN ((CONFIG_FRAME_SYNC_SIZE << SSC_FSLEN_SHIFT) & SSC_FSLEN_MASK) +#define EXTRA_FSLEN (CONFIG_EXTRA_FRAME_SYNC_SIZE << SSC_FSLEN_EXT) -static uint8_t play_buf1[CONFIG_PLAY_BUF_LEN]; -static uint8_t play_buf2[CONFIG_PLAY_BUF_LEN]; -// the buffer in PDC next is play_buf2 -volatile bool is_second_buf_next; +static void sam3_i2s_txStop(I2s *i2s) +{ + (void)i2s; + SSC_CR = BV(SSC_TXDIS); +} -uint8_t *i2s_getBuffer(unsigned buf_num) +static void sam3_i2s_txWait(I2s *i2s) { - LOG_INFO("getBuffer start\n"); - - if (i2s_isPlaying()) - { - ASSERT(0); - return 0; - } - - if (buf_num == I2S_SECOND_BUF) - return play_buf2; - else if (buf_num == I2S_FIRST_BUF) - return play_buf1; - else - return 0; + (void)i2s; } -uint8_t *i2s_getFreeBuffer(void) +static void sam3_i2s_txStart(I2s *i2s, void *buf, size_t len, size_t slice_len) { - // wait PDC transmission end - if (!(SSC_SR & BV(SSC_ENDTX))) - return 0; - - uint8_t *ret_buf = 0; - // the last time we got called, the second buffer was in PDC next - if (is_second_buf_next) - { - is_second_buf_next = false; - ret_buf = play_buf1; - } - // the last time the first buffer was in PDC next - else - { - is_second_buf_next = true; - ret_buf = play_buf2; - } - - if (ret_buf) - { - SSC_TNPR = (reg32_t) ret_buf; - SSC_TNCR = PDC_COUNT; - } - return ret_buf; + (void)i2s; + (void)buf; + (void)len; + (void)slice_len; } -void i2s_stop(void) +static void sam3_i2s_rxStop(I2s *i2s) { + (void)i2s; SSC_CR = BV(SSC_TXDIS); } +static void sam3_i2s_rxWait(I2s *i2s) +{ + (void)i2s; +} -bool i2s_start(void) +static void sam3_i2s_rxStart(I2s *i2s, void *buf, size_t len, size_t slice_len) { - /* Some time must pass between disabling and enabling again the transmission - * on SSC. A good empirical value seems >15 us. We try to avoid putting an - * explicit delay, instead we disable the transmitter when a sound finishes - * and hope that the delay has passed before we enter here again. - */ - SSC_CR = BV(SSC_TXDIS); - timer_delay(10); + (void)i2s; + (void)buf; + (void)len; + (void)slice_len; +} - SSC_PTCR = BV(PDC_PTCR_TXTDIS); - SSC_TPR = (reg32_t)play_buf1; - SSC_TCR = PDC_COUNT; - SSC_TNPR = (reg32_t)play_buf2; - SSC_TNCR = PDC_COUNT; - is_second_buf_next = true; - SSC_PTCR = BV(PDC_PTSR_TXTEN); +static bool sam3_i2s_isTxFinish(struct I2s *i2s) +{ + (void)i2s; + return false; +} - /* enable output */ - SSC_CR = BV(SSC_TXEN); +static bool sam3_i2s_isRxFinish(struct I2s *i2s) +{ + (void)i2s; + return false; +} - return true; +static void sam3_i2s_txBuf(struct I2s *i2s, void *buf, size_t len) +{ + (void)i2s; + (void)buf; + (void)len; } -#define BITS_PER_CHANNEL 16 -#define N_OF_CHANNEL 2 -// TODO: check the computed value? -/* The last parameter (2) is due to the hadware on at91sam7s. */ -#define MCK_DIV (CPU_FREQ / CONFIG_SAMPLE_FREQ / BITS_PER_CHANNEL / N_OF_CHANNEL / 2) +static void sam3_i2s_rxBuf(struct I2s *i2s, void *buf, size_t len) +{ + (void)i2s; + (void)buf; + (void)len; +} -#define CONFIG_DELAY 1 -#define CONFIG_PERIOD 15 -#define CONFIG_DATNB 1 -#define CONFIG_FSLEN 15 +static int sam3_i2s_write(struct I2s *i2s, uint32_t sample) +{ + (void)i2s; + while(!(SSC_SR & BV(SSC_TXRDY))); + SSC_THR = sample; + return 0; +} -#define DELAY ((CONFIG_DELAY << SSC_STTDLY_SHIFT) & SSC_STTDLY_MASK) -#define PERIOD ((CONFIG_PERIOD << (SSC_PERIOD_SHIFT)) & SSC_PERIOD_MASK) -#define DATNB ((CONFIG_DATNB << SSC_DATNB_SHIFT) & SSC_DATNB_MASK) -#define FSLEN ((CONFIG_FSLEN << SSC_FSLEN_SHIFT) & SSC_FSLEN_MASK) -#define SSC_DMA_IRQ_PRIORITY 5 +static uint32_t sam3_i2s_read(struct I2s *i2s) +{ + (void)i2s; + while(!(SSC_SR & BV(SSC_RXRDY))); + return SSC_RHR; +} +/* static DECLARE_ISR(irq_ssc) { } - -void i2s_init(void) +*/ +void i2s_init(I2s *i2s, int channel) { - SSC_PIO_PDR = BV(SSC_TK) | BV(SSC_TF) | BV(SSC_TD); - PIO_PERIPH_SEL(SSC_PORT, BV(SSC_TK) | BV(SSC_TF) | BV(SSC_TD), SSC_TRAN_PERIPH); + (void)channel; + i2s->ctx.write = sam3_i2s_write; + i2s->ctx.tx_buf = sam3_i2s_txBuf; + i2s->ctx.tx_isFinish = sam3_i2s_isTxFinish; + i2s->ctx.tx_start = sam3_i2s_txStart; + i2s->ctx.tx_wait = sam3_i2s_txWait; + i2s->ctx.tx_stop = sam3_i2s_txStop; + + i2s->ctx.read = sam3_i2s_read; + i2s->ctx.rx_buf = sam3_i2s_rxBuf; + i2s->ctx.rx_isFinish = sam3_i2s_isRxFinish; + i2s->ctx.rx_start = sam3_i2s_rxStart; + i2s->ctx.rx_wait = sam3_i2s_rxWait; + i2s->ctx.rx_stop = sam3_i2s_rxStop; + + DB(i2s->ctx._type = I2S_SAM3X;) + i2s->hw = &i2s_hw; + + PIOA_PDR = BV(SSC_TK) | BV(SSC_TF) | BV(SSC_TD); + PIO_PERIPH_SEL(PIOA_BASE, BV(SSC_TK) | BV(SSC_TF) | BV(SSC_TD), PIO_PERIPH_B); + PIOB_PDR = BV(SSC_RD) | BV(SSC_RF); + PIO_PERIPH_SEL(PIOB_BASE, BV(SSC_RD) | BV(SSC_RF), PIO_PERIPH_A); + + /* clock the ssc */ + pmc_periphEnable(SSC_ID); /* reset device */ - SSC_CR = BV(SSC_SWRST); + SSC_CR = BV(SSC_SWRST) | BV(SSC_TXDIS) | BV(SSC_RXDIS); /* Set transmission clock */ SSC_CMR = MCK_DIV & SSC_DIV_MASK; @@ -188,7 +193,7 @@ void i2s_init(void) * - generate frame sync each 2*(PERIOD + 1) tramit clock * - Receive start on falling edge RF */ - SSC_TCMR = SSC_CKS_DIV | SSC_CKO_TRAN | SSC_CKG_NONE | DELAY | PERIOD | SSC_START_FALL_F; + SSC_TCMR = SSC_CKS_DIV | SSC_CKO_CONT | SSC_CKG_NONE | DELAY | PERIOD | SSC_START_FALL_F; /* Set the transmission frame mode: * - data len DATALEN + 1 * - word per frame DATNB + 1 @@ -197,14 +202,14 @@ void i2s_init(void) * - MSB * - Frame sync output selection negative */ - SSC_TFMR = DATALEN | DATNB | FSLEN | BV(SSC_MSBF) | SSC_FSOS_NEGATIVE; + SSC_TFMR = DATALEN | DATNB | FSLEN | EXTRA_FSLEN | BV(SSC_MSBF) | SSC_FSOS_POSITIVE; - SSC_IDR = 0xFFFFFFFF; - sysirq_setHandler(INT_SSC, irq_ssc); - /* Clock DAC peripheral */ - pmc_periphEnable(SSC_ID); + // Receiver should start on TX and take the clock from TK + SSC_RCMR = SSC_CKS_CLK | BV(SSC_CKI) | SSC_CKO_CONT | SSC_CKG_NONE | DELAY | PERIOD | SSC_START_TX; + SSC_RFMR = DATALEN | DATNB | FSLEN | EXTRA_FSLEN | BV(SSC_MSBF) | SSC_FSOS_POSITIVE; - /* Enable SSC */ - SSC_CR = BV(SSC_TXEN); + + SSC_IDR = 0xFFFFFFFF; + SSC_CR = BV(SSC_TXEN) | BV(SSC_RXEN); }