X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fcortex-m3%2Fdrv%2Fmt29f_sam3.c;h=a0a7bfd36584e30d9549bd29cffa15e6b4b5b302;hb=f248bd5d8be37c741ef62386d82e4975723e09c3;hp=89095f94aeb06040bd60ac90838a0222ac37dfc9;hpb=734abc0f8ed652abddddedee6acf515954a5b13c;p=bertos.git diff --git a/bertos/cpu/cortex-m3/drv/mt29f_sam3.c b/bertos/cpu/cortex-m3/drv/mt29f_sam3.c index 89095f94..a0a7bfd3 100644 --- a/bertos/cpu/cortex-m3/drv/mt29f_sam3.c +++ b/bertos/cpu/cortex-m3/drv/mt29f_sam3.c @@ -46,7 +46,6 @@ #include #include -#include #include #include @@ -56,79 +55,299 @@ #include /* memcpy() */ +// Timeout for NAND operations in ms +#define MT29F_TMOUT 100 + +// NAND flash status codes +#define MT29F_STATUS_READY BV(6) +#define MT29F_STATUS_ERROR BV(0) + +// NAND flash commands +#define MT29F_CMD_READ_1 0x00 +#define MT29F_CMD_READ_2 0x30 +#define MT29F_CMD_COPYBACK_READ_1 0x00 +#define MT29F_CMD_COPYBACK_READ_2 0x35 +#define MT29F_CMD_COPYBACK_PROGRAM_1 0x85 +#define MT29F_CMD_COPYBACK_PROGRAM_2 0x10 +#define MT29F_CMD_RANDOM_OUT 0x05 +#define MT29F_CMD_RANDOM_OUT_2 0xE0 +#define MT29F_CMD_RANDOM_IN 0x85 +#define MT29F_CMD_READID 0x90 +#define MT29F_CMD_WRITE_1 0x80 +#define MT29F_CMD_WRITE_2 0x10 +#define MT29F_CMD_ERASE_1 0x60 +#define MT29F_CMD_ERASE_2 0xD0 +#define MT29F_CMD_STATUS 0x70 +#define MT29F_CMD_RESET 0xFF + +// Addresses for sending command, addresses and data bytes to flash +#define MT29F_CMD_ADDR 0x60400000 +#define MT29F_ADDR_ADDR 0x60200000 +#define MT29F_DATA_ADDR 0x60000000 + + +/* + * Translate flash page index plus a byte offset + * in the five address cycles format needed by NAND. + * + * Cycles in x8 mode as the MT29F2G08AAD + * CA = column addr, PA = page addr, BA = block addr + * + * Cycle I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 + * ------------------------------------------------------- + * First CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 + * Second LOW LOW LOW LOW CA11 CA10 CA9 CA8 + * Third BA7 BA6 PA5 PA4 PA3 PA2 PA1 PA0 + * Fourth BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8 + * Fifth LOW LOW LOW LOW LOW LOW LOW BA16 + */ +static void getAddrCycles(uint32_t page, size_t offset, uint32_t *cycle0, uint32_t *cycle1234) +{ + ASSERT(offset < MT29F_PAGE_SIZE); + + *cycle0 = offset & 0xff; + *cycle1234 = (page << 8) | ((offset >> 8) & 0xf); + + LOG_INFO("mt29f addr: %lx %lx\n", *cycle1234, *cycle0); +} + + +INLINE bool nfcIsBusy(void) +{ + return HWREG(NFC_CMD_BASE_ADDR + NFC_CMD_NFCCMD) & 0x8000000; +} + +INLINE bool isCmdDone(void) +{ + return SMC_SR & SMC_SR_CMDDONE; +} + +static bool waitReadyBusy(void) +{ + time_t start = timer_clock(); + + while (!(SMC_SR & SMC_SR_RB_EDGE0)) + { + cpu_relax(); + if (timer_clock() - start > MT29F_TMOUT) + { + LOG_INFO("mt29f: R/B timeout\n"); + return false; + } + } + + return true; +} + +/* + * Wait for transfer to complete until timeout. + * If transfer completes return true, false in case of timeout. + */ +static bool waitTransferComplete(void) +{ + time_t start = timer_clock(); + + while (!(SMC_SR & SMC_SR_XFRDONE)) + { + cpu_relax(); + if (timer_clock() - start > MT29F_TMOUT) + { + LOG_INFO("mt29f: xfer complete timeout\n"); + return false; + } + } + + return true; +} + -struct Mt29fHardware +/* + * Send command to NAND and wait for completion. + */ +static void sendCommand(uint32_t cmd, + int num_cycles, uint32_t cycle0, uint32_t cycle1234) { - int boh; -}; + reg32_t *cmd_addr; + + while (nfcIsBusy()); + if (num_cycles == 5) + SMC_ADDR = cycle0; -static size_t mt29f_readDirect(struct KBlock *blk, block_idx_t idx, void *buf, size_t offset, size_t size) + cmd_addr = (reg32_t *)(NFC_CMD_BASE_ADDR + cmd); + *cmd_addr = cycle1234; + + while (!isCmdDone()); +} + + +static bool isOperationComplete(void) { + uint8_t status; + + sendCommand( + NFC_CMD_NFCCMD | MT29F_CSID | NFC_CMD_ACYCLE_NONE | + MT29F_CMD_STATUS << 2, + 0, 0, 0); + + status = (uint8_t)HWREG(MT29F_DATA_ADDR); + return (status & MT29F_STATUS_READY) && !(status & MT29F_STATUS_ERROR); } -static size_t mt29f_writeDirect(struct KBlock *blk, block_idx_t idx, const void *_buf, size_t offset, size_t size) +static void chipReset(void) { + sendCommand( + NFC_CMD_NFCCMD | MT29F_CSID | NFC_CMD_ACYCLE_NONE | + MT29F_CMD_RESET << 2, + 0, 0, 0); + + waitReadyBusy(); } -static int mt29f_error(struct KBlock *blk) +/** + * Erase the whole block containing given page. + */ +int mt29f_blockErase(Mt29f *chip, uint32_t page) { - Mt29f *fls = FLASH_CAST(blk); + uint32_t cycle0; + uint32_t cycle1234; + + getAddrCycles(page, 0, &cycle0, &cycle1234); + + sendCommand( + NFC_CMD_NFCCMD | MT29F_CSID | NFC_CMD_ACYCLE_THREE | NFC_CMD_VCMD2 | + (MT29F_CMD_ERASE_2 << 10) | (MT29F_CMD_ERASE_1 << 2), + 3, 0, cycle1234 >> 8); + + waitReadyBusy(); + + if (!isOperationComplete()) + { + LOG_ERR("mt29f: error erasing block\n"); + chip->status |= MT29F_ERR_ERASE; + return -1; + } + + return 0; } -static void mt29f_clearerror(struct KBlock *blk) +/** + * Read Device ID and configuration codes. + */ +bool mt29f_getDevId(Mt29f *chip, uint8_t dev_id[5]) { - Mt29f *fls = FLASH_CAST(blk); + sendCommand( + NFC_CMD_NFCCMD | NFC_CMD_NFCEN | MT29F_CSID | NFC_CMD_ACYCLE_ONE | + MT29F_CMD_READID << 2, + 1, 0, 0); + + waitReadyBusy(); + if (!waitTransferComplete()) + { + LOG_ERR("mt29f: getDevId timeout\n"); + chip->status |= MT29F_ERR_RD_TMOUT; + return false; + } + + memcpy(dev_id, (void *)NFC_SRAM_BASE_ADDR, 5); + return true; } -static const KBlockVTable mt29f_buffered_vt = +size_t mt29f_pageRead(Mt29f *chip, uint32_t page, void *buf, size_t offset, size_t size) { - .readDirect = mt29f_readDirect, - .writeDirect = mt29f_writeDirect, + uint32_t cycle0; + uint32_t cycle1234; - .readBuf = kblock_swReadBuf, - .writeBuf = kblock_swWriteBuf, - .load = kblock_swLoad, - .store = kblock_swStore, + ASSERT(offset == 0); - .close = kblock_swClose, + LOG_INFO("mt29f_pageRead\n"); - .error = mt29f_error, - .clearerr = mt29f_clearerror, -}; + getAddrCycles(page, 0, &cycle0, &cycle1234); + sendCommand( + NFC_CMD_NFCCMD | NFC_CMD_NFCEN | MT29F_CSID | NFC_CMD_ACYCLE_FIVE | NFC_CMD_VCMD2 | + (MT29F_CMD_READ_2 << 10) | (MT29F_CMD_READ_1 << 2), + 5, cycle0, cycle1234); -static const KBlockVTable mt29f_unbuffered_vt = + waitReadyBusy(); + if (!waitTransferComplete()) + { + LOG_ERR("mt29f: read timeout\n"); + chip->status |= MT29F_ERR_RD_TMOUT; + return 0; + } + + memcpy(buf, (void *)NFC_SRAM_BASE_ADDR, size); + + return size; +} + + +size_t mt29f_pageWrite(Mt29f *chip, uint32_t page, const void *buf, size_t offset, size_t size) { - .readDirect = mt29f_readDirect, - .writeDirect = mt29f_writeDirect, + uint32_t cycle0; + uint32_t cycle1234; + + ASSERT(offset == 0); + + LOG_INFO("mt29f_pageWrite\n"); + + memcpy((void *)NFC_SRAM_BASE_ADDR, buf, size); - .close = kblock_swClose, + getAddrCycles(page, 0, &cycle0, &cycle1234); - .error = mt29f_error, - .clearerr = mt29f_clearerror, -}; + sendCommand( + NFC_CMD_NFCCMD | NFC_CMD_NFCWR | NFC_CMD_NFCEN | MT29F_CSID | NFC_CMD_ACYCLE_FIVE | + MT29F_CMD_WRITE_1 << 2, + 5, cycle0, cycle1234); + if (!waitTransferComplete()) + { + LOG_ERR("mt29f: write timeout\n"); + chip->status |= MT29F_ERR_WR_TMOUT; + return 0; + } -static struct Mt29fHardware mt29f_hw; -static uint8_t kblock_buf[MT29F_PAGE_SIZE]; + sendCommand( + NFC_CMD_NFCCMD | MT29F_CSID | NFC_CMD_ACYCLE_NONE | + MT29F_CMD_WRITE_2 << 2, + 0, 0, 0); + waitReadyBusy(); -static void common_init(Mt29f *fls) + if (!isOperationComplete()) + { + LOG_ERR("mt29f: error writing page\n"); + chip->status |= MT29F_ERR_WRITE; + return 0; + } + + return size; +} + + +int mt29f_error(Mt29f *chip) { - memset(fls, 0, sizeof(*fls)); - DB(fls->blk.priv.type = KBT_MT29F); + return chip->status; +} + - fls->hw = &mt29f_hw; +void mt29f_clearError(Mt29f *chip) +{ + chip->status = 0; +} - fls->blk.blk_size = MT29F_PAGE_SIZE; - fls->blk.blk_cnt = MT29F_SIZE / MT29F_PAGE_SIZE; - // TODO: put following stuff in hw_ file dependent (and configurable cs?) +static void initPio(Mt29f *chip) +{ + /* + * TODO: put following stuff in hw_ file dependent (and configurable cs?) + * Parameters for MT29F8G08AAD + */ pmc_periphEnable(PIOA_ID); pmc_periphEnable(PIOC_ID); pmc_periphEnable(PIOD_ID); @@ -146,7 +365,11 @@ static void common_init(Mt29f *fls) PIOD_PUER = MT29F_PINS_PORTD; pmc_periphEnable(SMC_SDRAMC_ID); +} + +static void initSmc(Mt29f *chip) +{ SMC_SETUP0 = SMC_SETUP_NWE_SETUP(0) | SMC_SETUP_NCS_WR_SETUP(0) | SMC_SETUP_NRD_SETUP(0) @@ -171,26 +394,29 @@ static void common_init(Mt29f *fls) SMC_MODE0 = SMC_MODE_READ_MODE | SMC_MODE_WRITE_MODE; + SMC_CFG = SMC_CFG_PAGESIZE_PS2048_64 + | SMC_CFG_EDGECTRL + | SMC_CFG_DTOMUL_X1048576 + | SMC_CFG_DTOCYC(0xF); + // Disable SMC interrupts, reset and enable NFC controller + SMC_IDR = ~0; + SMC_CTRL = 0; + SMC_CTRL = SMC_CTRL_NFCEN; + + // Enable ECC, 1 ECC per 256 bytes + SMC_ECC_CTRL = SMC_ECC_CTRL_SWRST; + SMC_ECC_MD = SMC_ECC_MD_ECC_PAGESIZE_PS2048_64 | SMC_ECC_MD_TYPCORREC_C256B; } -void mt29f_hw_init(Mt29f *fls, int flags) +void mt29f_init(Mt29f *chip) { - common_init(fls); - fls->blk.priv.vt = &mt29f_buffered_vt; - fls->blk.priv.flags |= KB_BUFFERED | KB_PARTIAL_WRITE; - fls->blk.priv.buf = kblock_buf; - - // Load the first block in the cache - void *start = 0x0; - memcpy(fls->blk.priv.buf, start, fls->blk.blk_size); -} + initPio(chip); + initSmc(chip); + mt29f_clearError(chip); -void mt29f_hw_initUnbuffered(Mt29f *fls, int flags) -{ - common_init(fls); - fls->blk.priv.vt = &mt29f_unbuffered_vt; + chipReset(); }