X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fcortex-m3%2Fdrv%2Fnand_sam3.c;h=85350cb761a58a5aa65804b39221b5f27e445a78;hb=78c0c32b36b62e3d8102d2803068186f52ff1d32;hp=cac51afdb3340e6a79690c251a8c7576372fedee;hpb=bcc879816c385dea470a0363a802934c498e71e4;p=bertos.git diff --git a/bertos/cpu/cortex-m3/drv/nand_sam3.c b/bertos/cpu/cortex-m3/drv/nand_sam3.c index cac51afd..85350cb7 100644 --- a/bertos/cpu/cortex-m3/drv/nand_sam3.c +++ b/bertos/cpu/cortex-m3/drv/nand_sam3.c @@ -30,21 +30,16 @@ * * --> * - * \brief NAND driver for SAM3's static memory controller. + * \brief NAND driver hardware implementation for SAM3's static memory controller. * * \author Stefano Fedrigo */ -#include "nand_sam3.h" #include #include -#include #include #include -#include /* cpu_relax() */ -#include - -#include /* memcpy, memset */ +#include // cpu_relax() /* @@ -89,6 +84,7 @@ bool nand_waitReadyBusy(UNUSED_ARG(Nand *, chip), time_t timeout) return true; } + /* * Wait for transfer to complete until timeout. * If transfer completes return true, false in case of timeout. @@ -163,19 +159,25 @@ uint8_t nand_getChipStatus(UNUSED_ARG(Nand *, chip)) } +/* + * Return pointer to buffer where data are read to or written from + * by nand_sendCommand(). + */ void *nand_dataBuffer(UNUSED_ARG(Nand *, chip)) { return (void *)NFC_SRAM_BASE_ADDR; } -bool nand_checkEcc(Nand *chip) +/* + * Extract ECC data from ECC_PRx registers. + */ +bool nand_checkEcc(UNUSED_ARG(Nand *, chip)) { uint32_t sr1 = SMC_ECC_SR1; if (sr1) { LOG_INFO("ECC error, ECC_SR1=0x%lx\n", sr1); - chip->status |= NAND_ERR_ECC; return false; } else @@ -201,6 +203,9 @@ void nand_computeEcc(UNUSED_ARG(Nand *, chip), } +/* + * Low-level hardware driver initialization. + */ void nand_hwInit(UNUSED_ARG(Nand *, chip)) { // FIXME: Parameters specific for MT29F8G08AAD