X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fcortex-m3%2Fdrv%2Fser_lm3s.c;h=b326a058bc9af98b0960275311f497788a0fffa5;hb=6447257f41c6d0f3d6b7a486e2683f930a5afdd3;hp=d24094dd0f0af0af3f9cb118566008a04ed72b98;hpb=341eb0f84a2592c0674ac67f2418b1db27e8d3ac;p=bertos.git diff --git a/bertos/cpu/cortex-m3/drv/ser_lm3s.c b/bertos/cpu/cortex-m3/drv/ser_lm3s.c index d24094dd..b326a058 100644 --- a/bertos/cpu/cortex-m3/drv/ser_lm3s.c +++ b/bertos/cpu/cortex-m3/drv/ser_lm3s.c @@ -36,7 +36,6 @@ */ #include /* for BV() */ -#include /* lm3s_busyWait() */ #include #include #include @@ -58,6 +57,40 @@ struct CM3Serial /* Forward declaration */ static struct CM3Serial UARTDesc[SER_CNT]; +/* GPIO descriptor for UART pins */ +struct gpio_uart_info +{ + /* Sysctl */ + uint32_t sysctl; + /* GPIO base address register */ + uint32_t base; + /* Pin(s) bitmask */ + uint8_t pins; +}; + +/* Table to retrieve GPIO pins configuration to work as UART pins */ +static const struct gpio_uart_info gpio_uart[SER_CNT] = +{ + /* UART0 */ + { + .base = GPIO_PORTA_BASE, + .pins = BV(1) | BV(0), + .sysctl = SYSCTL_RCGC2_GPIOA, + }, + /* UART1 */ + { + .base = GPIO_PORTD_BASE, + .pins = BV(3) | BV(2), + .sysctl = SYSCTL_RCGC2_GPIOD, + }, + /* UART2 */ + { + .base = GPIO_PORTG_BASE, + .pins = BV(1) | BV(0), + .sysctl = SYSCTL_RCGC2_GPIOG, + }, +}; + /* Clear the flags register */ INLINE void lm3s_uartClear(uint32_t base) { @@ -124,11 +157,11 @@ void lm3s_uartInit(int port) /* Enable the peripheral clock */ SYSCTL_RCGC1_R |= reg_clock; - SYSCTL_RCGC2_R |= SYSCTL_RCGC2_GPIOA; + SYSCTL_RCGC2_R |= gpio_uart[port].sysctl; lm3s_busyWait(512); - /* Set GPIO A0 and A1 as UART pins */ - lm3s_gpioPinConfig(GPIO_PORTA_BASE, BV(0) | BV(1), + /* Configure GPIO pins to work as UART pins */ + lm3s_gpioPinConfig(gpio_uart[port].base, gpio_uart[port].pins, GPIO_DIR_MODE_HW, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); /* Set serial param: 115.200 bps, no parity */