X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fcortex-m3%2Fdrv%2Fser_stm32.c;h=0b8c4f32acfed9162846cd1d52b8d97f00f6d18e;hb=563795df4180aaceb7d69306551230c98fbca879;hp=315329bd8adae1391dd438ea4c98b737afefe039;hpb=e70c73c7eedf8644b88a66acacf913335e3395a9;p=bertos.git

diff --git a/bertos/cpu/cortex-m3/drv/ser_stm32.c b/bertos/cpu/cortex-m3/drv/ser_stm32.c
index 315329bd..0b8c4f32 100644
--- a/bertos/cpu/cortex-m3/drv/ser_stm32.c
+++ b/bertos/cpu/cortex-m3/drv/ser_stm32.c
@@ -72,8 +72,8 @@ struct gpio_uart_info
 	uint32_t rx_pin;
 	uint32_t tx_pin;
 	/* Sysctl */
-	uint32_t sysctl;
-	uint32_t sysctl1;
+	uint32_t sysctl_gpio;
+	uint32_t sysctl_usart;
 
 };
 
@@ -85,25 +85,27 @@ static const struct gpio_uart_info gpio_uart[SER_CNT] =
 		.base = GPIOA_BASE,
 		.rx_pin = GPIO_USART1_RX_PIN,
 		.tx_pin = GPIO_USART1_TX_PIN,
-		.sysctl = RCC_APB2_GPIOA,
-		.sysctl1 = RCC_APB2_USART1,
+		.sysctl_gpio = RCC_APB2_GPIOA,
+		.sysctl_usart = RCC_APB2_USART1,
 	},
 	/* UART2 */
 	{
 		.base = GPIOA_BASE,
 		.rx_pin = GPIO_USART2_RX_PIN,
 		.tx_pin = GPIO_USART2_TX_PIN,
-		.sysctl = RCC_APB2_GPIOA,
-		.sysctl1 = RCC_APB1_USART2,
+		.sysctl_gpio = RCC_APB2_GPIOA,
+		.sysctl_usart = RCC_APB1_USART2,
 	},
+#if CPU_CM3_STM32F103RB || CPU_CM3_STM32F103RE
 	/* UART3 */
 	{
 		.base = GPIOB_BASE,
 		.rx_pin = GPIO_USART3_RX_PIN,
 		.tx_pin = GPIO_USART3_TX_PIN,
-		.sysctl = RCC_APB2_GPIOB,
-		.sysctl1 = RCC_APB1_USART3,
+		.sysctl_gpio = RCC_APB2_GPIOB,
+		.sysctl_usart = RCC_APB1_USART3,
 	},
+#endif
 };
 
 #define USART1_PORT                0
@@ -145,22 +147,20 @@ void stm32_uartInit(int port)
 {
 	struct stm32_usart *base = (struct stm32_usart *)UARTDesc[port].base;
 
-	kprintf("init port[%d]cnt[%d]\n", port, SER_CNT);
 	ASSERT(port >= 0 && port < SER_CNT);
 
 	/* Enable clocking on AFIO */
 	RCC->APB2ENR |= RCC_APB2_AFIO;
+	RCC->APB2ENR |= gpio_uart[port].sysctl_gpio;
 
 	/* Configure USART pins */
 	if (port == USART1_PORT)
 	{
-		RCC->APB2ENR |=  gpio_uart[port].sysctl;
-		RCC->APB2ENR |=  gpio_uart[port].sysctl1;
+		RCC->APB2ENR |=  gpio_uart[port].sysctl_usart;
 	}
 	else
 	{
-		RCC->APB1ENR |=  gpio_uart[port].sysctl;
-		RCC->APB1ENR |=  gpio_uart[port].sysctl1;
+		RCC->APB1ENR |=  gpio_uart[port].sysctl_usart;
 	}
 
 	stm32_gpioPinConfig((struct stm32_gpio *)gpio_uart[port].base,  gpio_uart[port].tx_pin,
@@ -170,9 +170,9 @@ void stm32_uartInit(int port)
 				GPIO_MODE_IN_FLOATING, GPIO_SPEED_50MHZ);
 
 	/* Clear control registry */
-	base->CR2 = 0; //CR2_CLEAR_MASK;
-	base->CR1 = 0; //CR1_CLEAR_MASK;
-	base->CR3 = 0; //CR3_CLEAR_MASK;
+	base->CR2 = 0;
+	base->CR1 = 0;
+	base->CR3 = 0;
 	base->SR = 0;
 
 	/* Set serial param: 115.200 bps, no parity */
@@ -183,9 +183,6 @@ void stm32_uartInit(int port)
 	/* Enable trasmision and receiver */
 	base->CR1 |= (BV(CR1_TE) | BV(CR1_RE));
 
-
-	kprintf("INIT[%02x]\n", (uint8_t)base->SR); \
-
 }
 
 static bool tx_sending(struct SerialHardware *_hw)
@@ -221,7 +218,7 @@ static void uart_irq_tx(int port)
 		 * Disable TX empty interrupts if there're no more
 		 * characters to transmit.
 		 */
-		base->CR1 &= ~BV(7);
+		base->CR1 &= ~BV(CR1_TXEIE);
 		UARTDesc[port].sending = false;
 	}
 	else
@@ -237,12 +234,17 @@ static void uart_common_irq_handler(int port)
 
 	/* Read and clear the IRQ status */
 	status = base->SR;
+
+	/* Check hw errors */
+	ser_handles[port]->status = status &
+		(BV(SR_ORE) | BV(SR_FE) | BV(SR_PE) | BV(SR_NE));
+
 	/* Process the IRQ */
-	if (status & BV(5))
+	if (status & BV(CR1_RXNEIE))
 	{
 		uart_irq_rx(port);
 	}
-	if (status & (BV(7) | BV(6)))
+	if (status & (BV(CR1_TXEIE) | BV(CR1_TCIE)))
 	{
 		uart_irq_tx(port);
 	}
@@ -255,14 +257,14 @@ static void stm32_uartIRQEnable(int port, sysirq_handler_t handler)
 	/* Register the IRQ handler */
 	sysirq_setHandler(UARTDesc[port].irq, handler);
 
-	base->CR1 |= BV(5);
+	base->CR1 |= BV(CR1_RXNEIE);
 }
 
 static void stm32_uartIRQDisable(int port)
 {
 	struct stm32_usart *base = (struct stm32_usart *)UARTDesc[port].base;
 
-	base->CR1 &= ~(BV(5) | USART_FLAG_TXE);
+	base->CR1 &= ~(BV(CR1_RXNEIE) | USART_FLAG_TXE);
 }
 
 
@@ -289,9 +291,8 @@ static void stm32_uartIRQDisable(int port)
 		stm32_uartPutChar(USART ## port ## _BASE, fifo_pop(txfifo));	\
 		if (!fifo_isempty(txfifo))					\
 		{								\
-			kputs("tx_en_irq\n"); \
 			hw->sending = true;	 \
-			base->CR1 |= BV(7); \
+			base->CR1 |= BV(CR1_TXEIE); \
 		} \
 	}									\
 										\
@@ -338,7 +339,9 @@ static void stm32_uartIRQDisable(int port)
 /* UART port instances */
 UART_PORT(1)
 UART_PORT(2)
+#if CPU_CM3_STM32F103RB || CPU_CM3_STM32F103RE
 UART_PORT(3)
+#endif
 
 static struct CM3Serial UARTDesc[SER_CNT] =
 {
@@ -366,6 +369,7 @@ static struct CM3Serial UARTDesc[SER_CNT] =
 		.base = USART2_BASE,
 		.irq = USART2_IRQHANDLER,
 	},
+#if CPU_CM3_STM32F103RB || CPU_CM3_STM32F103RE
 	{
 		.hw = {
 			.table = &USART3_VT,
@@ -378,6 +382,7 @@ static struct CM3Serial UARTDesc[SER_CNT] =
 		.base = USART3_BASE,
 		.irq = USART3_IRQHANDLER,
 	},
+#endif
 };
 
 struct SerialHardware *ser_hw_getdesc(int port)