X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fcortex-m3%2Fhw%2Finit_cm3.c;h=b67900fccd0aefb16123efac696c9019c9233d2d;hb=b12629e93f75e4d8d0d750452d96d803f54489be;hp=079f08a31728acfd35feff4b0f11a8a895b3792d;hpb=9550884ef08501d68bda54d7ed3f41ccc24694eb;p=bertos.git diff --git a/bertos/cpu/cortex-m3/hw/init_cm3.c b/bertos/cpu/cortex-m3/hw/init_cm3.c index 079f08a3..b67900fc 100644 --- a/bertos/cpu/cortex-m3/hw/init_cm3.c +++ b/bertos/cpu/cortex-m3/hw/init_cm3.c @@ -35,23 +35,22 @@ * \author Andrea Righi */ +#include "cfg/cfg_proc.h" /* CONFIG_KERN_PREEMPT */ +#include "switch_ctx_cm3.h" + #include -#include /* CONFIG_KERN_PREEMPT */ -#include #include + #include /* PAUSE */ #include /* IRQ_DISABLE */ #include + #include -#include "switch_ctx_cm3.h" +#include -#if CPU_CM3_LM3S -#include -#include -#elif CPU_CM3_STM32 -#include -#include -#endif +#include + +#include extern size_t __text_end, __data_start, __data_end, __bss_start, __bss_end; @@ -65,35 +64,13 @@ void __init2(void) */ IRQ_DISABLE; -#if CPU_CM3_LM3S - /* - * PLL may not function properly at default LDO setting. - * - * Description: - * - * In designs that enable and use the PLL module, unstable device - * behavior may occur with the LDO set at its default of 2.5 volts or - * below (minimum of 2.25 volts). Designs that do not use the PLL - * module are not affected. - * - * Workaround: Prior to enabling the PLL module, it is recommended that - * the default LDO voltage setting of 2.5 V be adjusted to 2.75 V using - * the LDO Power Control (LDOPCTL) register. - * - * Silicon Revision Affected: A1, A2 - * - * See also: Stellaris LM3S1968 A2 Errata documentation. - */ - if (REVISION_IS_A1 | REVISION_IS_A2) - HWREG(SYSCTL_LDOPCTL) = SYSCTL_LDOPCTL_2_75V; -#endif /* Set the appropriate clocking configuration */ clock_init(); /* Initialize IRQ vector table in RAM */ sysirq_init(); -#if CONFIG_KERN_PREEMPT +#if (CONFIG_KERN && CONFIG_KERN_PREEMPT) /* * Voluntary context switch handler. *