X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fcortex-m3%2Fhw%2Finit_lm3s.c;fp=bertos%2Fcpu%2Fcortex-m3%2Fhw%2Finit_lm3s.c;h=eaa05edfd6fe3db4235e1b9e437012a4842be28b;hb=a61181f8614fe8257dc21bf1762a380165932348;hp=0000000000000000000000000000000000000000;hpb=39fa28bf9a32a1ad99c631c20b38ecacd5c0626f;p=bertos.git diff --git a/bertos/cpu/cortex-m3/hw/init_lm3s.c b/bertos/cpu/cortex-m3/hw/init_lm3s.c new file mode 100644 index 00000000..eaa05edf --- /dev/null +++ b/bertos/cpu/cortex-m3/hw/init_lm3s.c @@ -0,0 +1,78 @@ +/** + * \file + * + * + * \brief Cortex-M3 architecture's entry point + * + * \author Andrea Righi + */ + +#include +#include +#include /* PAUSE */ +#include "drv/irq_lm3s.h" +#include "drv/clock_lm3s.h" +#include "io/lm3s.h" + +extern size_t __text_end, __data_start, __data_end, __bss_start, __bss_end; + +extern void __init2(void); + +/* Architecture's entry point */ +void __init2(void) +{ + /* + * PLL may not function properly at default LDO setting. + * + * Description: + * + * In designs that enable and use the PLL module, unstable device + * behavior may occur with the LDO set at its default of 2.5 volts or + * below (minimum of 2.25 volts). Designs that do not use the PLL + * module are not affected. + * + * Workaround: Prior to enabling the PLL module, it is recommended that + * the default LDO voltage setting of 2.5 V be adjusted to 2.75 V using + * the LDO Power Control (LDOPCTL) register. + * + * Silicon Revision Affected: A1, A2 + * + * See also: Stellaris LM3S1968 A2 Errata documentation. + */ + if (REVISION_IS_A1 | REVISION_IS_A2) + HWREG(SYSCTL_LDOPCTL) = SYSCTL_LDOPCTL_2_75V; + + /* Set the appropriate clocking configuration */ + clock_set_rate(); + + /* Initialize IRQ vector table in RAM */ + sysirq_init(); +}