X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fcortex-m3%2Fio%2Fsam3.h;h=3d007d50b2a037ae8a20e5a36f8ae0a3fe0bfd17;hb=6970f4233dd70293d45f2df4406c581128e887dc;hp=beba679391074cd0bc1ceea4d17bf0fa1f0cf125;hpb=7dff07b2a890ada8bdce1f4a89f143b621660835;p=bertos.git

diff --git a/bertos/cpu/cortex-m3/io/sam3.h b/bertos/cpu/cortex-m3/io/sam3.h
index beba6793..3d007d50 100644
--- a/bertos/cpu/cortex-m3/io/sam3.h
+++ b/bertos/cpu/cortex-m3/io/sam3.h
@@ -137,26 +137,10 @@
 	#error undefined U(S)ART_PORTS for this cpu
 #endif
 
-/* PDC registers */
-#define PERIPH_RPR_OFF  0x100  // Receive Pointer Register.
-#define PERIPH_RCR_OFF  0x104  // Receive Counter Register.
-#define PERIPH_TPR_OFF  0x108  // Transmit Pointer Register.
-#define PERIPH_TCR_OFF  0x10C  // Transmit Counter Register.
-#define PERIPH_RNPR_OFF 0x110  // Receive Next Pointer Register.
-#define PERIPH_RNCR_OFF 0x114  // Receive Next Counter Register.
-#define PERIPH_TNPR_OFF 0x118  // Transmit Next Pointer Register.
-#define PERIPH_TNCR_OFF 0x11C  // Transmit Next Counter Register.
-#define PERIPH_PTCR_OFF 0x120  // PDC Transfer Control Register.
-#define PERIPH_PTSR_OFF 0x124  // PDC Transfer Status Register.
-
-#define PDC_RXTEN  0
-#define PDC_RXTDIS 1
-#define PDC_TXTEN  8
-#define PDC_TXTDIS 9
-
-
 #include "sam3_sysctl.h"
+#include "sam3_pdc.h"
 #include "sam3_pmc.h"
+#include "sam3_dmac.h"
 #include "sam3_smc.h"
 #include "sam3_sdramc.h"
 #include "sam3_ints.h"
@@ -173,6 +157,9 @@
 #include "sam3_dacc.h"
 #include "sam3_tc.h"
 #include "sam3_twi.h"
+#include "sam3_ssc.h"
+#include "sam3_hsmci.h"
+#include "sam3_chipid.h"
 
 /**
  * U(S)ART I/O pins
@@ -304,5 +291,65 @@
 	#define TWI1_TWCK   25
 #endif
 
+#if CPU_CM3_SAM3X
+	#define SSC_PORT            PIOA_BASE
+	#define SSC_PIO_PDR         PIOA_PDR
+	#define SSC_RECV_PERIPH     PIO_PERIPH_A
+	#define SSC_TRAN_PERIPH     PIO_PERIPH_B
+	#define SSC_RD              18
+	#define SSC_RF              17
+	#define SSC_RK              19
+	#define SSC_TD              16
+	#define SSC_TF              15
+	#define SSC_TK              14
+#elif CPU_CM3_SAM3N
+	#define SSC_PORT            /* None! */
+	#define SSC_PIO_PDR         /* None! */
+	#define SSC_RECV_PERIPH     /* None! */
+	#define SSC_TRAN_PERIPH     /* None! */
+	#define SSC_RD              /* None! */
+	#define SSC_RF              /* None! */
+	#define SSC_RK              /* None! */
+	#define SSC_TD              /* None! */
+	#define SSC_TF              /* None! */
+	#define SSC_TK              /* None! */
+#elif CPU_CM3_SAM3S
+	#define SSC_PORT            PIOA_BASE
+	#define SSC_PIO_PDR         PIOA_PDR
+	#define SSC_RECV_PERIPH     PIO_PERIPH_A
+	#define SSC_TRAN_PERIPH     PIO_PERIPH_A
+	#define SSC_RD              18
+	#define SSC_RF              20
+	#define SSC_RK              19
+	#define SSC_TD              17
+	#define SSC_TF              15
+	#define SSC_TK              16
+#elif CPU_CM3_SAM3U
+	#define SSC_PORT            PIOA_BASE
+	#define SSC_PIO_PDR         PIOA_PDR
+	#define SSC_RECV_PERIPH     PIO_PERIPH_A
+	#define SSC_TRAN_PERIPH     PIO_PERIPH_A
+	#define SSC_RD              27
+	#define SSC_RF              31
+	#define SSC_RK              29
+	#define SSC_TD              26
+	#define SSC_TF              30
+	#define SSC_TK              28
+#else
+	#error no ssc pins are defined for this cpu
+#endif
+
+
+#if CPU_CM3_SAM3X8
+	#define FLASH_MEM_SIZE          0x80000UL ///< Internal flash memory size
+	#define FLASH_PAGE_SIZE_BYTES         256 ///< Size of cpu flash memory page in bytes
+	#define FLASH_BANKS_NUM                 2 ///< Number of flash banks
+	#define FLASH_PAGES_FOR_BANK         1024 ///< Number pages for each bank
+	#define FLASH_BASE                    0x0
+#else
+	#error no internal flash info are defined for this cpu
+#endif
+
+
 /*\}*/
 #endif /* SAM3_H */