X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fcortex-m3%2Fio%2Fsam3.h;h=beba679391074cd0bc1ceea4d17bf0fa1f0cf125;hb=b7165529c0174f9bc5a1f4f51a4e405f202e48d5;hp=8e66d1e81cbab4c85fe690bbf7132cdcee97ee61;hpb=c49471ed35076929444a0a90899df4a6ee00a49a;p=bertos.git

diff --git a/bertos/cpu/cortex-m3/io/sam3.h b/bertos/cpu/cortex-m3/io/sam3.h
index 8e66d1e8..beba6793 100644
--- a/bertos/cpu/cortex-m3/io/sam3.h
+++ b/bertos/cpu/cortex-m3/io/sam3.h
@@ -127,6 +127,16 @@
 #define USART_HAS_PDC  1
 #define SPI_HAS_PDC    1
 
+#if CPU_CM3_SAM3X || CPU_CM3_SAM3U
+	#define USART_PORTS    1
+	#define UART_PORTS     4
+#elif CPU_CM3_SAM3N || CPU_CM3_SAM3S
+	#define USART_PORTS    2
+	#define UART_PORTS     2
+#else
+	#error undefined U(S)ART_PORTS for this cpu
+#endif
+
 /* PDC registers */
 #define PERIPH_RPR_OFF  0x100  // Receive Pointer Register.
 #define PERIPH_RCR_OFF  0x104  // Receive Counter Register.
@@ -147,6 +157,8 @@
 
 #include "sam3_sysctl.h"
 #include "sam3_pmc.h"
+#include "sam3_smc.h"
+#include "sam3_sdramc.h"
 #include "sam3_ints.h"
 #include "sam3_pio.h"
 #include "sam3_nvic.h"
@@ -155,27 +167,87 @@
 #include "sam3_spi.h"
 #include "sam3_flash.h"
 #include "sam3_wdt.h"
+#include "sam3_emac.h"
+#include "sam3_rstc.h"
+#include "sam3_adc.h"
+#include "sam3_dacc.h"
+#include "sam3_tc.h"
+#include "sam3_twi.h"
 
 /**
- * UART I/O pins
+ * U(S)ART I/O pins
  */
 /*\{*/
 #if CPU_CM3_SAM3U
-	#define RXD0   11
-	#define TXD0   12
+	#define UART0_PORT   PIOA_BASE
+	#define USART0_PORT  PIOA_BASE
+	#define USART1_PORT  PIOA_BASE
+	#define USART2_PORT  PIOA_BASE
+	#define USART3_PORT  PIOC_BASE
+
+	#define UART0_PERIPH   PIO_PERIPH_A
+	#define USART0_PERIPH  PIO_PERIPH_A
+	#define USART1_PERIPH  PIO_PERIPH_A
+	#define USART2_PERIPH  PIO_PERIPH_A
+	#define USART3_PERIPH  PIO_PERIPH_B
+
+	#define URXD0   11
+	#define UTXD0   12
+	#define RXD0    19
+	#define TXD0    18
+	#define RXD1    21
+	#define TXD1    20
+	#define RXD2    23
+	#define TXD2    22
+	#define RXD3    13
+	#define TXD3    12
 #elif CPU_CM3_SAM3X
-	#define RXD0    8
-	#define TXD0    9
-#else
-	#define RXD0    9
-	#define TXD0   10
-	#define RXD1    2
-	#define TXD1    3
+	#define UART0_PORT   PIOA_BASE
+	#define USART0_PORT  PIOA_BASE
+	#define USART1_PORT  PIOA_BASE
+	#define USART2_PORT  PIOB_BASE
+	#define USART3_PORT  PIOD_BASE
+
+	#define UART0_PERIPH   PIO_PERIPH_A
+	#define USART0_PERIPH  PIO_PERIPH_A
+	#define USART1_PERIPH  PIO_PERIPH_A
+	#define USART2_PERIPH  PIO_PERIPH_A
+	#define USART3_PERIPH  PIO_PERIPH_B
+
+	#define URXD0    8
+	#define UTXD0    9
+	#define RXD0    10
+	#define TXD0    11
+	#define RXD1    12
+	#define TXD1    13
+	#define RXD2    21
+	#define TXD2    20
+	#define RXD3     5
+	#define TXD3     4
+#elif CPU_CM3_SAM3N || CPU_CM3_SAM3S
+	#define UART0_PORT   PIOA_BASE
+	#define UART1_PORT   PIOB_BASE
+	#define USART0_PORT  PIOA_BASE
+	#define USART1_PORT  PIOA_BASE
+
+	#define UART0_PERIPH   PIO_PERIPH_A
+	#define UART1_PERIPH   PIO_PERIPH_A
+	#define USART0_PERIPH  PIO_PERIPH_A
+	#define USART1_PERIPH  PIO_PERIPH_A
+
+	#define URXD0    9
+	#define UTXD0   10
+	#define URXD1    2
+	#define UTXD1    3
+	#define RXD0     5
+	#define TXD0     6
+	#define RXD1    21
+	#define TXD1    22
 #endif
 /*\}*/
 
 /**
- * PIO I/O pins
+ * SPI I/O pins
  */
 /*\{*/
 #if CPU_CM3_SAM3U
@@ -191,5 +263,46 @@
 	#define SPI0_MOSI   13
 	#define SPI0_MISO   12
 #endif
+/*\}*/
+
+/**
+ * TWI I/O pins
+ */
+/*\{*/
+#if CPU_CM3_SAM3X
+	#define TWI0_PORT   PIOA_BASE
+	#define TWI1_PORT   PIOA_BASE
+
+	#define TWI0_PERIPH  PIO_PERIPH_A
+	#define TWI1_PERIPH  PIO_PERIPH_A
+
+	#define TWI0_TWD    17
+	#define TWI0_TWCK   18
+	#define TWI1_TWD    12
+	#define TWI1_TWCK   13
+#elif CPU_CM3_SAM3N || CPU_CM3_SAM3S
+	#define TWI0_PORT   PIOA_BASE
+	#define TWI1_PORT   PIOB_BASE
+
+	#define TWI0_PERIPH  PIO_PERIPH_A
+	#define TWI1_PERIPH  PIO_PERIPH_A
+
+	#define TWI0_TWD    3
+	#define TWI0_TWCK   4
+	#define TWI1_TWD    4
+	#define TWI1_TWCK   5
+#elif CPU_CM3_SAM3U
+	#define TWI0_PORT   PIOA_BASE
+	#define TWI1_PORT   PIOA_BASE
+
+	#define TWI0_PERIPH  PIO_PERIPH_A
+	#define TWI1_PERIPH  PIO_PERIPH_A
+
+	#define TWI0_TWD    9
+	#define TWI0_TWCK   10
+	#define TWI1_TWD    24
+	#define TWI1_TWCK   25
+#endif
+
 /*\}*/
 #endif /* SAM3_H */