X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fcortex-m3%2Fio%2Fsam3.h;h=bedb1ce68fae36385f6496dbf6a54dce735d60a6;hb=4ef5df302b6a0dc984ec503ec4f3cf6ed2be48d3;hp=54aedad01328abe29642e6fec781f514a9bc9345;hpb=90c889315ecdc605fce8d1b257cc76779e45e2c5;p=bertos.git diff --git a/bertos/cpu/cortex-m3/io/sam3.h b/bertos/cpu/cortex-m3/io/sam3.h index 54aedad0..bedb1ce6 100644 --- a/bertos/cpu/cortex-m3/io/sam3.h +++ b/bertos/cpu/cortex-m3/io/sam3.h @@ -137,26 +137,10 @@ #error undefined U(S)ART_PORTS for this cpu #endif -/* PDC registers */ -#define PERIPH_RPR_OFF 0x100 // Receive Pointer Register. -#define PERIPH_RCR_OFF 0x104 // Receive Counter Register. -#define PERIPH_TPR_OFF 0x108 // Transmit Pointer Register. -#define PERIPH_TCR_OFF 0x10C // Transmit Counter Register. -#define PERIPH_RNPR_OFF 0x110 // Receive Next Pointer Register. -#define PERIPH_RNCR_OFF 0x114 // Receive Next Counter Register. -#define PERIPH_TNPR_OFF 0x118 // Transmit Next Pointer Register. -#define PERIPH_TNCR_OFF 0x11C // Transmit Next Counter Register. -#define PERIPH_PTCR_OFF 0x120 // PDC Transfer Control Register. -#define PERIPH_PTSR_OFF 0x124 // PDC Transfer Status Register. - -#define PDC_RXTEN 0 -#define PDC_RXTDIS 1 -#define PDC_TXTEN 8 -#define PDC_TXTDIS 9 - - #include "sam3_sysctl.h" +#include "sam3_pdc.h" #include "sam3_pmc.h" +#include "sam3_dmac.h" #include "sam3_smc.h" #include "sam3_sdramc.h" #include "sam3_ints.h" @@ -171,6 +155,11 @@ #include "sam3_rstc.h" #include "sam3_adc.h" #include "sam3_dacc.h" +#include "sam3_tc.h" +#include "sam3_twi.h" +#include "sam3_ssc.h" +#include "sam3_hsmci.h" +#include "sam3_chipid.h" /** * U(S)ART I/O pins @@ -245,7 +234,7 @@ /*\}*/ /** - * PIO I/O pins + * SPI I/O pins */ /*\{*/ #if CPU_CM3_SAM3U @@ -262,4 +251,148 @@ #define SPI0_MISO 12 #endif /*\}*/ + +/** + * TWI I/O pins + */ +/*\{*/ +#if CPU_CM3_SAM3X + #define TWI0_PORT PIOA_BASE + #define TWI1_PORT PIOA_BASE + + #define TWI0_PERIPH PIO_PERIPH_A + #define TWI1_PERIPH PIO_PERIPH_A + + #define TWI0_TWD 17 + #define TWI0_TWCK 18 + #define TWI1_TWD 12 + #define TWI1_TWCK 13 +#elif CPU_CM3_SAM3N || CPU_CM3_SAM3S + #define TWI0_PORT PIOA_BASE + #define TWI1_PORT PIOB_BASE + + #define TWI0_PERIPH PIO_PERIPH_A + #define TWI1_PERIPH PIO_PERIPH_A + + #define TWI0_TWD 3 + #define TWI0_TWCK 4 + #define TWI1_TWD 4 + #define TWI1_TWCK 5 +#elif CPU_CM3_SAM3U + #define TWI0_PORT PIOA_BASE + #define TWI1_PORT PIOA_BASE + + #define TWI0_PERIPH PIO_PERIPH_A + #define TWI1_PERIPH PIO_PERIPH_A + + #define TWI0_TWD 9 + #define TWI0_TWCK 10 + #define TWI1_TWD 24 + #define TWI1_TWCK 25 +#endif + +#if CPU_CM3_SAM3X + #define SSC_PORT PIOA_BASE + #define SSC_PIO_PDR PIOA_PDR + #define SSC_RECV_PERIPH PIO_PERIPH_A + #define SSC_TRAN_PERIPH PIO_PERIPH_B + #define SSC_RD 18 + #define SSC_RF 17 + #define SSC_RK 19 + #define SSC_TD 16 + #define SSC_TF 15 + #define SSC_TK 14 +#elif CPU_CM3_SAM3N + #define SSC_PORT /* None! */ + #define SSC_PIO_PDR /* None! */ + #define SSC_RECV_PERIPH /* None! */ + #define SSC_TRAN_PERIPH /* None! */ + #define SSC_RD /* None! */ + #define SSC_RF /* None! */ + #define SSC_RK /* None! */ + #define SSC_TD /* None! */ + #define SSC_TF /* None! */ + #define SSC_TK /* None! */ +#elif CPU_CM3_SAM3S + #define SSC_PORT PIOA_BASE + #define SSC_PIO_PDR PIOA_PDR + #define SSC_RECV_PERIPH PIO_PERIPH_A + #define SSC_TRAN_PERIPH PIO_PERIPH_A + #define SSC_RD 18 + #define SSC_RF 20 + #define SSC_RK 19 + #define SSC_TD 17 + #define SSC_TF 15 + #define SSC_TK 16 +#elif CPU_CM3_SAM3U + #define SSC_PORT PIOA_BASE + #define SSC_PIO_PDR PIOA_PDR + #define SSC_RECV_PERIPH PIO_PERIPH_A + #define SSC_TRAN_PERIPH PIO_PERIPH_A + #define SSC_RD 27 + #define SSC_RF 31 + #define SSC_RK 29 + #define SSC_TD 26 + #define SSC_TF 30 + #define SSC_TK 28 +#else + #error no ssc pins are defined for this cpu +#endif + + +#if CPU_CM3_SAM3X8 + #define FLASH_MEM_SIZE 0x80000UL ///< Internal flash memory size + #define FLASH_PAGE_SIZE_BYTES 256 ///< Size of cpu flash memory page in bytes + #define FLASH_BANKS_NUM 2 ///< Number of flash banks + #define FLASH_PAGES_FOR_BANK 1024 ///< Number pages for each bank + #define FLASH_BASE 0x80000 ///< Start address for bank 0 +#elif CPU_CM3_SAM3U4 + #define FLASH_MEM_SIZE 0x40000UL ///< Internal flash memory size + #define FLASH_PAGE_SIZE_BYTES 256 ///< Size of cpu flash memory page in bytes + #define FLASH_BANKS_NUM 2 ///< Number of flash banks + #define FLASH_PAGES_FOR_BANK 512 ///< Number pages for each bank + #define FLASH_BASE 0x80000 ///< Start address for bank 0 +#elif CPU_CM3_SAM3N4 || CPU_CM3_SAM3S4 + #define FLASH_MEM_SIZE 0x40000UL ///< Internal flash memory size + #define FLASH_PAGE_SIZE_BYTES 256 ///< Size of cpu flash memory page in bytes + #define FLASH_BANKS_NUM 1 ///< Number of flash banks + #define FLASH_PAGES_FOR_BANK 1024 ///< Number pages for each bank + #define FLASH_BASE 0x400000 ///< Start address for bank 0 +#else + #error no internal flash info are defined for this cpu +#endif + + +#if CPU_CM3_SAM3X8 + // Port B + #define PHY_REFCLK_XT2_BIT 0 + #define PHY_TXEN_BIT 1 + #define PHY_TXD0_BIT 2 + #define PHY_TXD1_BIT 3 + #define PHY_RXDV_TESTMODE_BIT 4 + #define PHY_RXD0_AD0_BIT 5 + #define PHY_RXD1_AD1_BIT 6 + #define PHY_RXER_RXD4_RPTR_BIT 7 + #define PHY_MDC_BIT 8 + #define PHY_MDIO_BIT 9 + // Port A + #define PHY_MDINTR_BIT 5 +#elif (CPU_CM3_SAM3U || CPU_CM3_SAM3N) + /* No ethernet interface is present on this cpu */ +#else + #error No MII/RMII PHY pins interface was define for select CPU. +#endif + +#define PHY_MII_PINS_PORTB \ + BV(PHY_REFCLK_XT2_BIT) \ + | BV(PHY_TXEN_BIT) \ + | BV(PHY_TXD0_BIT) \ + | BV(PHY_TXD1_BIT) \ + | BV(PHY_RXD0_AD0_BIT) \ + | BV(PHY_RXD1_AD1_BIT) \ + | BV(PHY_RXER_RXD4_RPTR_BIT) \ + | BV(PHY_MDC_BIT) \ + | BV(PHY_MDIO_BIT) + + #endif /* SAM3_H */