X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fcortex-m3%2Fio%2Fsam3_adc.h;h=c855dc850d9bff03b97b006d27ce0b4c40874361;hb=f1fab319eb3fe91c157b3a9564841aef62a03554;hp=6f761b142ee87f03f0e244eb6e8291952d4970a7;hpb=5d6e1feb6eb171345f5e36258bbc9763c580e1f9;p=bertos.git diff --git a/bertos/cpu/cortex-m3/io/sam3_adc.h b/bertos/cpu/cortex-m3/io/sam3_adc.h index 6f761b14..c855dc85 100644 --- a/bertos/cpu/cortex-m3/io/sam3_adc.h +++ b/bertos/cpu/cortex-m3/io/sam3_adc.h @@ -34,6 +34,8 @@ * * SAM3 Analog to Digital Converter. * + * $WIZ$ + * */ @@ -64,12 +66,12 @@ #define ADC_TRGSEL_TIOA0 0x00000000 ///< TIOA output of the timer counter channel 0. #define ADC_TRGSEL_TIOA1 0x00000002 ///< TIOA output of the timer counter channel 1. #define ADC_TRGSEL_TIOA2 0x00000004 ///< TIOA output of the timer counter channel 2. -#define ADC_TRGSEL_PWM0 0x0000000A ///< PWM Event Line 0. -#define ADC_TRGSEL_PWM1 0x0000000C ///< PWM Event Line 1. +#define ADC_TRGSEL_PWM0 0x0000000A ///< PWM Event Line 0. +#define ADC_TRGSEL_PWM1 0x0000000C ///< PWM Event Line 1. #define ADC_LOWRES 4 ///< Resolution 0: 12-bit, 1: 10-bit. #define ADC_SLEEP 5 ///< Sleep mode. - +#define ADC_FREERUN 7 ///< Freerun. /** * Prescaler rate selection. @@ -81,38 +83,59 @@ /** * Start up timer. */ -#define ADC_STARTUP_MASK 0x000F0000 ///< Start up timer mask. -#define ADC_STARTUP_SHIFT 16 ///< Start up timer shift. -#define ADC_SUT0 0 ///< 0 period of ADCClock. -#define ADC_SUT1 1 ///< 8 period of ADCClock. -#define ADC_SUT2 2 ///< 16 period of ADCClock. -#define ADC_SUT3 3 ///< 24 period of ADCClock. -#define ADC_SUT4 4 ///< 64 period of ADCClock. -#define ADC_SUT5 5 ///< 80 period of ADCClock. -#define ADC_SUT6 6 ///< 96 period of ADCClock. -#define ADC_SUT7 7 ///< 112 period of ADCClock. -#define ADC_SUT8 8 ///< 512 period of ADCClock. -#define ADC_SUT9 9 ///< 576 period of ADCClock. -#define ADC_SUT10 10 ///< 640 period of ADCClock. -#define ADC_SUT11 11 ///< 704 period of ADCClock. -#define ADC_SUT12 12 ///< 768 period of ADCClock. -#define ADC_SUT13 13 ///< 832 period of ADCClock. -#define ADC_SUT14 14 ///< 832 period of ADCClock. -#define ADC_SUT15 15 ///< 896 period of ADCClock. -#define ADC_SUT16 16 ///< 960 period of ADCClock. - - -/** - * Sample & hold time. - */ -#define ADC_SHTIME_MASK 0x0F000000 ///< Sample & hold time mask. -#define ADC_SHTIME_SHIFT 20 ///< Sample & hold time shift. -#define ADC_AST3 0 ///< 3 period of ADCClock -#define ADC_AST5 1 ///< 5 period of ADCClock -#define ADC_AST9 2 ///< 9 period of ADCClock -#define ADC_AST17 3 ///< 17 period of ADCClock +#define ADC_STARTUP_MASK 0x000F0000 ///< Start up timer mask. +#define ADC_STARTUP_SHIFT 16 ///< Start up timer shift. + +/** + * Start up timer. + * $WIZ$ sam3_adc_sut = "ADC_SUT0","ADC_SUT8","ADC_SUT16","ADC_SUT24","ADC_SUT64","DC_SUT80","ADC_SUT96","ADC_SUT112","ADC_SUT512","ADC_SUT576","ADC_SUT640","ADC_SUT704","ADC_SUT768","ADC_SUT832","ADC_SUT896","ADC_SUT960" + * \{ + */ +#define ADC_SUT0 0 ///< 0 period of ADCClock. +#define ADC_SUT8 1 ///< 8 period of ADCClock. +#define ADC_SUT16 2 ///< 16 period of ADCClock. +#define ADC_SUT24 3 ///< 24 period of ADCClock. +#define ADC_SUT64 4 ///< 64 period of ADCClock. +#define ADC_SUT80 5 ///< 80 period of ADCClock. +#define ADC_SUT96 6 ///< 96 period of ADCClock. +#define ADC_SUT112 7 ///< 112 period of ADCClock. +#define ADC_SUT512 8 ///< 512 period of ADCClock. +#define ADC_SUT576 9 ///< 576 period of ADCClock. +#define ADC_SUT640 10 ///< 640 period of ADCClock. +#define ADC_SUT704 11 ///< 704 period of ADCClock. +#define ADC_SUT768 12 ///< 768 period of ADCClock. +#define ADC_SUT832 13 ///< 832 period of ADCClock. +#define ADC_SUT896 14 ///< 896 period of ADCClock. +#define ADC_SUT960 15 ///< 896 period of ADCClock. +/** \} */ + +/** + * Analog Settling Time. + * $WIZ$ sam3_adc_stt = "ADC_AST3", "ADC_AST5", "ADC_AST9", "ADC_AST17" + */ +#define ADC_SETTLING_MASK 0x00300000 ///< Analog Settling Time mask. +#define ADC_SETTLING_SHIFT 20 ///< Analog Settling Time shift. +#define ADC_AST3 0 ///< 3 period of ADCClock +#define ADC_AST5 1 ///< 5 period of ADCClock +#define ADC_AST9 2 ///< 9 period of ADCClock +#define ADC_AST17 3 ///< 17 period of ADCClock + +/** + * Tracking Time. + * Tracking Time = (TRACKTIM + 1) * ADCClock periods. + */ +#define ADC_TRACKTIM_MASK 0x0F000000 ///< Tracking Time mask. +#define ADC_TRACKTIM_SHIFT 24 ///< Tracking Time shift. + +/** + * Transfer Period. + * Transfer Period = (TRANSFER * 2 + 3) ADCClock periods. + */ +#define ADC_TRANSFER_MASK 0x30000000 ///< Transfer Period mask. +#define ADC_TRANSFER_SHIFT 28 ///< Transfer Period shift. /* \} */ + /** * ADC channel enable register */ @@ -131,7 +154,15 @@ #define ADC_CHSR_OFF 0x00000018 ///< Channel status register offeset. #define ADC_CHSR (*((reg32_t *)(ADC_BASE + ADC_CHSR_OFF))) ///< Channel status register address. -#define ADC_CH_MASK 0x000000FF ///< Channel mask. + +/** + * ADC status register + */ +#define ADC_SR_OFF 0x0000001C ///< Status register offeset. +#define ADC_SR (*((reg32_t *)(ADC_BASE + ADC_SR_OFF))) ///< Status register address. + + +#define ADC_CH_MASK 0x0000FFFF ///< Channel mask. #define ADC_CH0 0 ///< Channel 0 #define ADC_CH1 1 ///< Channel 1 #define ADC_CH2 2 ///< Channel 2 @@ -192,10 +223,32 @@ /** * ADC last convert data register. + * \{ */ #define ADC_LCDR_OFF 0x00000020 ///< Last converted data register offeset. #define ADC_LCDR (*((reg32_t *)(ADC_BASE + ADC_LCDR_OFF))) ///< Last converted RAW data register. #define ADC_LDATA (ADC_LCDR & 0xFFF) ///< Last data converted register. #define ADC_CHNB ((ADC_LCDR & 0xF000) >> 12) ///< Channel number. +/* \} */ + + +/** + * ADC Channel data register. + * \{ + */ +#define ADC_CDR_OFF 0x00000050 ///< Channel data register offeset. +#define ADC_CDR (*((reg32_t *)(ADC_BASE + ADC_CDR_OFF))) ///< Channel data register. +/* \} */ + + +/** + * ADC Analog Control register. + * \{ + */ +#define ADC_ACR_OFF 0x00000094 ///< Analog control register offeset. +#define ADC_ACR (*((reg32_t *)(ADC_BASE + ADC_ACR_OFF))) ///< Analog control register. +#define ADC_TSON 4 ///< Temperature Sensor On. +#define ADC_TEMPERATURE_CH 15 ///< Channel where is the internal sensor temperature +/* \} */ #endif /* SAM3_ADC_H */