X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fcortex-m3%2Fio%2Fsam3_dacc.h;h=e2071dd72ed3654a4608bc71981413dfb62dd548;hb=21b75b7cc0266b3b1ec244daf19b587cfeb3e5d8;hp=0848a3b2e317904784cb84df3b0ce7dcbbe3b826;hpb=f9cbe9ae977a6c3d79031899ac0faecf91a6cfc4;p=bertos.git

diff --git a/bertos/cpu/cortex-m3/io/sam3_dacc.h b/bertos/cpu/cortex-m3/io/sam3_dacc.h
index 0848a3b2..e2071dd7 100644
--- a/bertos/cpu/cortex-m3/io/sam3_dacc.h
+++ b/bertos/cpu/cortex-m3/io/sam3_dacc.h
@@ -41,6 +41,8 @@
 #ifndef SAM3_DACC_H
 #define SAM3_DACC_H
 
+#include <io/cm3.h>
+
 /** DACC registers base. */
 #define DACC_BASE               0x400C8000
 
@@ -165,8 +167,8 @@
 /**
  * DACC Interrupt disable register
  */
-#define DACC_IMR_OFF             0x0000002C     ///< Interrupt disable register offeset.
-#define DACC_IMR          (*((reg32_t*) (DACC_BASE + DACC_IMR_OFF)))    ///< Interrupt disable register address.
+#define DACC_IMR_OFF             0x0000002C     ///< Interrupt mask register offeset.
+#define DACC_IMR          (*((reg32_t*) (DACC_BASE + DACC_IMR_OFF)))    ///< Interrupt mask register address.
 
 /**
  * DACC Interrupt status register
@@ -176,7 +178,7 @@
 
 #define DACC_TXRDY                        0     ///< Transmit ready interrupt
 #define DACC_EOC                          1     ///< End of conversion interrupt
-#define DACC_ENDTX                        2     ///< End of transmit buffer interrupt
+#define DACC_ENDTX                        2     ///< End of DMA Interrupt Flag
 #define DACC_TXBUFE                       3     ///< Transmit buffer empty interrupt
 
 
@@ -184,35 +186,16 @@
  * DMA controller for DACC
  * DACC PDC register.
  */
-#define DACC_RPR_OFF                     0x100 ///< Receive Pointer Register.
-#define DACC_RPR        (*((reg32_t*) (DACC_BASE + DACC_RPR_OFF)))    ///< Receive Pointer Register.
-
-#define DACC_RCR_OFF                     0x104 ///< Receive Counter Register.
-#define DACC_RCR       (*((reg32_t*) (DACC_BASE + DACC_RCR_OFF)))   ///<  Receive Counter Register.
-
-#define DACC_TPR_OFF                     0x108 ///< Transmit Pointer Register.
-#define DACC_TPR       (*((reg32_t*) (DACC_BASE + DACC_TPR_OFF)))   ///<  Transmit Pointer Register.
-
-#define DACC_TCR_OFF                     0x10C ///< Transmit Counter Register.
-#define DACC_TCR       (*((reg32_t*) (DACC_BASE + DACC_TCR_OFF)))   ///< Transmit Counter Register.
-
-#define DACC_RNPR_OFF                    0x110 ///< Receive Next Pointer Register.
-#define DACC_RNPR      (*((reg32_t*) (DACC_BASE + DACC_RNPR_OFF)))   ///< Receive Next Pointer Register.
-
-#define DACC_RNCR_OFF                    0x114 ///< Receive Next Counter Register.
-#define DACC_RNCR      (*((reg32_t*) (DACC_BASE + DACC_RNCR_OFF)))   ///< Receive Next Counter Register.
-
-#define DACC_TNPR_OFF                    0x118 ///< Transmit Next Pointer Register.
-#define DACC_TNPR      (*((reg32_t*) (DACC_BASE + DACC_TNPR_OFF)))   ///< Transmit Next Pointer Register.
-
-#define DACC_TNCR_OFF                    0x11C ///< Transmit Next Counter Register.
-#define DACC_TNCR      (*((reg32_t*) (DACC_BASE + DACC_TNCR_OFF)))   ///< Transmit Next Counter Register.
-
-#define DACC_PTCR_OFF                    0x120 ///< Transfer Control Register.
-#define DACC_PTCR      (*((reg32_t*) (DACC_BASE + DACC_PTCR_OFF)))  ///< Transfer Control Register.
-
-#define DACC_PTSR_OFF                    0x124 ///< Transfer Status Register.
-#define DACC_PTSR      (*((reg32_t*) (DACC_BASE + DACC_PTSR_OFF)))    ///< Transfer Status Register.
+#define DACC_RPR       (*((reg32_t*) (DACC_BASE + PERIPH_RPR_OFF)))  ///< Receive Pointer Register.
+#define DACC_RCR       (*((reg32_t*) (DACC_BASE + PERIPH_RCR_OFF)))  ///<  Receive Counter Register.
+#define DACC_TPR       (*((reg32_t*) (DACC_BASE + PERIPH_TPR_OFF)))  ///<  Transmit Pointer Register.
+#define DACC_TCR       (*((reg32_t*) (DACC_BASE + PERIPH_TCR_OFF)))  ///< Transmit Counter Register.
+#define DACC_RNPR      (*((reg32_t*) (DACC_BASE + PERIPH_RNPR_OFF))) ///< Receive Next Pointer Register.
+#define DACC_RNCR      (*((reg32_t*) (DACC_BASE + PERIPH_RNCR_OFF))) ///< Receive Next Counter Register.
+#define DACC_TNPR      (*((reg32_t*) (DACC_BASE + PERIPH_TNPR_OFF))) ///< Transmit Next Pointer Register.
+#define DACC_TNCR      (*((reg32_t*) (DACC_BASE + PERIPH_TNCR_OFF))) ///< Transmit Next Counter Register.
+#define DACC_PTCR      (*((reg32_t*) (DACC_BASE + PERIPH_PTCR_OFF))) ///< Transfer Control Register.
+#define DACC_PTSR      (*((reg32_t*) (DACC_BASE + PERIPH_PTSR_OFF))) ///< Transfer Status Register.
 
 
 #define DACC_PTCR_RXTEN               0  ///< DACC_PTCR  Receiver Transfer Enable.