X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fcortex-m3%2Fio%2Fsam3_flash.h;h=44cae6a53464eb0838be2cce086e78a1c842fade;hb=b4ba8a4cb5ff2100559c5e9fa54fd203623b6037;hp=74257a8d2de75c863952cb21ccc0f154af81154f;hpb=c796e2e7baf75175e4c14311f0aa0080d7f65862;p=bertos.git

diff --git a/bertos/cpu/cortex-m3/io/sam3_flash.h b/bertos/cpu/cortex-m3/io/sam3_flash.h
index 74257a8d..44cae6a5 100644
--- a/bertos/cpu/cortex-m3/io/sam3_flash.h
+++ b/bertos/cpu/cortex-m3/io/sam3_flash.h
@@ -30,16 +30,22 @@
  *
  * -->
  *
- * \brief ATSAM3 enhanced embedded flash controller definitions.
+ * \brief Atmel SAM3 enhanced embedded flash controller definitions.
  */
 
 #ifndef SAM3_FLASH_H
 #define SAM3_FLASH_H
 
 /**
- * EEFC base register address.
+ * EEFC base registers addresses.
  */
-#define EEFC_BASE  0x400E0A00
+/*\{*/
+#define EEFC0_BASE  0x400E0A00
+#ifdef CPU_CM3_SAM3X
+	#define EEFC1_BASE  0x400E0C00
+#endif
+/*\}*/
+
 
 /**
  * EFC register offsets.
@@ -55,10 +61,17 @@
  * EEFC registers.
  */
 /*\{*/
-#define EEFC_FMR  (*((reg32_t *)(EEFC_BASE + EEFC_FMR_OFF)))  ///< Flash Mode Register
-#define EEFC_FCR  (*((reg32_t *)(EEFC_BASE + EEFC_FCR_OFF)))  ///< Flash Command Register
-#define EEFC_FSR  (*((reg32_t *)(EEFC_BASE + EEFC_FSR_OFF)))  ///< Flash Status Register
-#define EEFC_FRR  (*((reg32_t *)(EEFC_BASE + EEFC_FRR_OFF)))  ///< Flash Result Register
+#define EEFC0_FMR  (*((reg32_t *)(EEFC0_BASE + EEFC_FMR_OFF)))  ///< Flash Mode Register
+#define EEFC0_FCR  (*((reg32_t *)(EEFC0_BASE + EEFC_FCR_OFF)))  ///< Flash Command Register
+#define EEFC0_FSR  (*((reg32_t *)(EEFC0_BASE + EEFC_FSR_OFF)))  ///< Flash Status Register
+#define EEFC0_FRR  (*((reg32_t *)(EEFC0_BASE + EEFC_FRR_OFF)))  ///< Flash Result Register
+
+#ifdef CPU_CM3_SAM3X
+	#define EEFC1_FMR  (*((reg32_t *)(EEFC1_BASE + EEFC_FMR_OFF)))  ///< Flash Mode Register
+	#define EEFC1_FCR  (*((reg32_t *)(EEFC1_BASE + EEFC_FCR_OFF)))  ///< Flash Command Register
+	#define EEFC1_FSR  (*((reg32_t *)(EEFC1_BASE + EEFC_FSR_OFF)))  ///< Flash Status Register
+	#define EEFC1_FRR  (*((reg32_t *)(EEFC1_BASE + EEFC_FRR_OFF)))  ///< Flash Result Register
+#endif
 /*\}*/