X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fcortex-m3%2Fio%2Fsam3_flash.h;h=a35a31fc2ef50832da1238fe25944e32c7f228e8;hb=f1fab319eb3fe91c157b3a9564841aef62a03554;hp=74257a8d2de75c863952cb21ccc0f154af81154f;hpb=c796e2e7baf75175e4c14311f0aa0080d7f65862;p=bertos.git

diff --git a/bertos/cpu/cortex-m3/io/sam3_flash.h b/bertos/cpu/cortex-m3/io/sam3_flash.h
index 74257a8d..a35a31fc 100644
--- a/bertos/cpu/cortex-m3/io/sam3_flash.h
+++ b/bertos/cpu/cortex-m3/io/sam3_flash.h
@@ -30,16 +30,22 @@
  *
  * -->
  *
- * \brief ATSAM3 enhanced embedded flash controller definitions.
+ * \brief Atmel SAM3 enhanced embedded flash controller definitions.
  */
 
 #ifndef SAM3_FLASH_H
 #define SAM3_FLASH_H
 
 /**
- * EEFC base register address.
+ * EEFC base registers addresses.
  */
-#define EEFC_BASE  0x400E0A00
+/*\{*/
+#define EEFC0_BASE  0x400E0A00
+#ifdef CPU_CM3_SAM3X
+	#define EEFC1_BASE  0x400E0C00
+#endif
+/*\}*/
+
 
 /**
  * EFC register offsets.
@@ -55,10 +61,17 @@
  * EEFC registers.
  */
 /*\{*/
-#define EEFC_FMR  (*((reg32_t *)(EEFC_BASE + EEFC_FMR_OFF)))  ///< Flash Mode Register
-#define EEFC_FCR  (*((reg32_t *)(EEFC_BASE + EEFC_FCR_OFF)))  ///< Flash Command Register
-#define EEFC_FSR  (*((reg32_t *)(EEFC_BASE + EEFC_FSR_OFF)))  ///< Flash Status Register
-#define EEFC_FRR  (*((reg32_t *)(EEFC_BASE + EEFC_FRR_OFF)))  ///< Flash Result Register
+#define EEFC0_FMR  (*((reg32_t *)(EEFC0_BASE + EEFC_FMR_OFF)))  ///< Flash Mode Register
+#define EEFC0_FCR  (*((reg32_t *)(EEFC0_BASE + EEFC_FCR_OFF)))  ///< Flash Command Register
+#define EEFC0_FSR  (*((reg32_t *)(EEFC0_BASE + EEFC_FSR_OFF)))  ///< Flash Status Register
+#define EEFC0_FRR  (*((reg32_t *)(EEFC0_BASE + EEFC_FRR_OFF)))  ///< Flash Result Register
+
+#ifdef CPU_CM3_SAM3X
+	#define EEFC1_FMR  (*((reg32_t *)(EEFC1_BASE + EEFC_FMR_OFF)))  ///< Flash Mode Register
+	#define EEFC1_FCR  (*((reg32_t *)(EEFC1_BASE + EEFC_FCR_OFF)))  ///< Flash Command Register
+	#define EEFC1_FSR  (*((reg32_t *)(EEFC1_BASE + EEFC_FSR_OFF)))  ///< Flash Status Register
+	#define EEFC1_FRR  (*((reg32_t *)(EEFC1_BASE + EEFC_FRR_OFF)))  ///< Flash Result Register
+#endif
 /*\}*/
 
 
@@ -78,14 +91,26 @@
  * Defines for bit fields in EEFC_FCR register.
  */
 /*\{*/
-#define EEFC_FCR_FCMD_MASK    0xff                        ///< Flash Command
-#define EEFC_FCR_FCMD(value)  (EEFC_FCR_FCMD_MASK & (value))
+#define EFC_FCR_FCMD_MASK     0x000000FF      ///< Flash command mask.
+#define EFC_FCR_FCMD_GETD     0x00000000      ///< Get flash Descriptor.
+#define EFC_FCR_FCMD_WP       0x00000001      ///< Write page.
+#define EFC_FCR_FCMD_WPL      0x00000002      ///< Write page and lock.
+#define EFC_FCR_FCMD_EWP      0x00000003      ///< Erase page and write page.
+#define EFC_FCR_FCMD_EWPL     0x00000004      ///< Erase page and write page then lock.
+#define EFC_FCR_FCMD_EA       0x00000005      ///< Erase all.
+#define EFC_FCR_FCMD_SLB      0x00000008      ///< Set lock bit.
+#define EFC_FCR_FCMD_CLB      0x00000009      ///< Clear lock bit.
+#define EFC_FCR_FCMD_GLB      0x0000000A      ///< Get lock bit.
+#define EFC_FCR_FCMD_SGPB     0x0000000B      ///< Set GPNVM bit.
+#define EFC_FCR_FCMD_CGPB     0x0000000C      ///< Clear GPNVM bit.
+#define EFC_FCR_FCMD_GGPB     0x0000000D      ///< Get GPNVM bit.
+#define EFC_FCR_FCMD_STUI     0x0000000E      ///< Start read uniqune identifier.
+#define EFC_FCR_FCMD_SPUI     0x0000000F      ///< Stop read uniqune identifier.
+#define EFC_FCR_FCMD_GCALB    0x00000010      ///< Get CALIB bit.
 #define EEFC_FCR_FARG_SHIFT   8
 #define EEFC_FCR_FARG_MASK    (0xffff << EEFC_FCR_FARG_SHIFT) ///< Flash Command Argument
 #define EEFC_FCR_FARG(value)  (EEFC_FCR_FARG_MASK & ((value) << EEFC_FCR_FARG_SHIFT))
-#define EEFC_FCR_FKEY_SHIFT   24
-#define EEFC_FCR_FKEY_MASK    (0xff << EEFC_FCR_FKEY_SHIFT)   ///< Flash Writing Protection Key
-#define EEFC_FCR_FKEY(value)  (EEFC_FCR_FKEY_MASK & ((value) << EEFC_FCR_FKEY_SHIFT))
+#define EEFC_FCR_FKEY          0x5A000000      ///< Writing protect key.
 /*\}*/
 
 /**