X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fcortex-m3%2Fio%2Fsam3_hsmci.h;h=ec3408113416abd20c2f85566a6c359e32069f37;hb=8a5cb391f6130a8e8de0ae5323ce7004054327f2;hp=f75fd11265bd5190e236e9b066b2411dc2ed17e1;hpb=69f325286f17e01521047e9aed1c61fd94c3330c;p=bertos.git

diff --git a/bertos/cpu/cortex-m3/io/sam3_hsmci.h b/bertos/cpu/cortex-m3/io/sam3_hsmci.h
index f75fd112..ec340811 100644
--- a/bertos/cpu/cortex-m3/io/sam3_hsmci.h
+++ b/bertos/cpu/cortex-m3/io/sam3_hsmci.h
@@ -53,6 +53,9 @@
 #define HSMCI_BLKR          (*((reg32_t *)(HSMCI_BASE + 0x018))) ///< (Hsmci Offset: 0x18) Block Register
 #define HSMCI_CSTOR         (*((reg32_t *)(HSMCI_BASE + 0x01C))) ///< (Hsmci Offset: 0x1C) Completion Signal Timeout Register
 #define HSMCI_RSPR          (*((reg32_t *)(HSMCI_BASE + 0x020))) ///< (Hsmci Offset: 0x20) Response Register
+#define HSMCI_RSPR1         (*((reg32_t *)(HSMCI_BASE + 0x024))) ///< (Hsmci Offset: 0x24) Response Register
+#define HSMCI_RSPR2         (*((reg32_t *)(HSMCI_BASE + 0x028))) ///< (Hsmci Offset: 0x28) Response Register
+#define HSMCI_RSPR3         (*((reg32_t *)(HSMCI_BASE + 0x02C))) ///< (Hsmci Offset: 0x2C) Response Register
 #define HSMCI_RDR           (*((reg32_t *)(HSMCI_BASE + 0x030))) ///< (Hsmci Offset: 0x30) Receive Data Register
 #define HSMCI_TDR           (*((reg32_t *)(HSMCI_BASE + 0x034))) ///< (Hsmci Offset: 0x34) Transmit Data Register
 #define HSMCI_SR            (*((reg32_t *)(HSMCI_BASE + 0x040))) ///< (Hsmci Offset: 0x40) Status Register
@@ -160,6 +163,7 @@
 #define   HSMCI_BLKR_BCNT_BYTE         0x4 ///< (HSMCI_BLKR) SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.Values from 0x200 to 0xFFFF are forbidden.
 #define   HSMCI_BLKR_BCNT_BLOCK        0x5 ///< (HSMCI_BLKR) SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.Values from 0x200 to 0xFFFF are forbidden.
 #define   HSMCI_BLKR_BLKLEN_MASK       0xffff0000 ///< (HSMCI_BLKR) Data Block Length
+#define   HSMCI_BLKR_BLKLEN_SHIFT      16
 
 
 /* HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register */