X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fcortex-m3%2Fio%2Fsam3_ints.h;h=3c6bce856981b676c356b301e2281ab02e185a61;hb=9525bb5f7e0bf15bd0b11a21055adf804c6aa478;hp=422ff5113be1d3de9c460ff7ce9ea7e0d086f4c9;hpb=666f80bddb3d83383dee8f572b626690e81e3b18;p=bertos.git diff --git a/bertos/cpu/cortex-m3/io/sam3_ints.h b/bertos/cpu/cortex-m3/io/sam3_ints.h index 422ff511..3c6bce85 100644 --- a/bertos/cpu/cortex-m3/io/sam3_ints.h +++ b/bertos/cpu/cortex-m3/io/sam3_ints.h @@ -26,53 +26,121 @@ * invalidate any other reasons why the executable file might be covered by * the GNU General Public License. * - * Copyright 2010 Develer S.r.l. (http://www.develer.com/) + * Copyright 2010,2011 Develer S.r.l. (http://www.develer.com/) * * --> * - * \brief AT91SAM3 interrupt definitions. + * \brief SAM3 interrupt definitions. */ #ifndef SAM3_INTS_H #define SAM3_INTS_H /** - * Defines for the interrupt assignments. + * Defines for the fault assignments. */ /*\{*/ -#define INT_SUPC 0 ///< Supply Controller (SUPC) -#define INT_RSTC 1 ///< Reset Controller (RSTC) -#define INT_RTC 2 ///< Real Time Clock (RTC) -#define INT_RTT 3 ///< Real Time Timer (RTT) -#define INT_WDT 4 ///< Watchdog Timer (WDT) -#define INT_PMC 5 ///< Power Management Controller (PMC) -#define INT_EFC 6 ///< Enhanced Flash Controller (EFC) -#define INT_UART0 8 ///< UART 0 (UART0) -#define INT_UART1 9 ///< UART 1 (UART1) -#define INT_PIOA 11 ///< Parallel I/O Controller A (PIOA) -#define INT_PIOB 12 ///< Parallel I/O Controller B (PIOB) -#define INT_PIOC 13 ///< Parallel I/O Controller C (PIOC) -#define INT_USART0 14 ///< USART 0 (USART0) -#define INT_USART1 15 ///< USART 1 (USART1) -#define INT_TWI0 19 ///< Two Wire Interface 0 (TWI0) -#define INT_TWI1 20 ///< Two Wire Interface 1 (TWI1) -#define INT_SPI 21 ///< Serial Peripheral Interface (SPI) -#define INT_TC0 23 ///< Timer/Counter 0 (TC0) -#define INT_TC1 24 ///< Timer/Counter 1 (TC1) -#define INT_TC2 25 ///< Timer/Counter 2 (TC2) -#define INT_TC3 26 ///< Timer/Counter 3 (TC3) -#define INT_TC4 27 ///< Timer/Counter 4 (TC4) -#define INT_TC5 28 ///< Timer/Counter 5 (TC5) -#define INT_ADC 29 ///< Analog To Digital Converter (ADC) -#define INT_DACC 30 ///< Digital To Analog Converter (DACC) -#define INT_PWM 31 ///< Pulse Width Modulation (PWM) +#define FAULT_NMI 2 ///< NMI fault +#define FAULT_HARD 3 ///< Hard fault +#define FAULT_MPU 4 ///< MPU fault +#define FAULT_BUS 5 ///< Bus fault +#define FAULT_USAGE 6 ///< Usage fault +#define FAULT_SVCALL 11 ///< SVCall +#define FAULT_DEBUG 12 ///< Debug monitor +#define FAULT_PENDSV 14 ///< PendSV +#define FAULT_SYSTICK 15 ///< System Tick /*\}*/ /** - * Total number of interrupts. + * Defines for the interrupt assignments. */ /*\{*/ -#define NUM_INTERRUPTS 32 +#define INT_PERIPH_BASE 16 + +#if CPU_CM3_SAM3N + #define INT_SUPC (INT_PERIPH_BASE + SUPC_ID) + #define INT_RSTC (INT_PERIPH_BASE + RSTC_ID) + #define INT_RTC (INT_PERIPH_BASE + RTC_ID) + #define INT_RTT (INT_PERIPH_BASE + RTT_ID) + #define INT_WDT (INT_PERIPH_BASE + WDT_ID) + #define INT_PMC (INT_PERIPH_BASE + PMC_ID) + #define INT_EFC (INT_PERIPH_BASE + EFC_ID) + #define INT_UART0 (INT_PERIPH_BASE + UART0_ID) + #define INT_UART1 (INT_PERIPH_BASE + UART1_ID) + #define INT_PIOA (INT_PERIPH_BASE + PIOA_ID) + #define INT_PIOB (INT_PERIPH_BASE + PIOB_ID) + #define INT_PIOC (INT_PERIPH_BASE + PIOC_ID) + #define INT_US0 (INT_PERIPH_BASE + US0_ID) + #define INT_US1 (INT_PERIPH_BASE + US1_ID) + #define INT_TWI0 (INT_PERIPH_BASE + TWI0_ID) + #define INT_TWI1 (INT_PERIPH_BASE + TWI1_ID) + #define INT_SPI0 (INT_PERIPH_BASE + SPI0_ID) + #define INT_TC0 (INT_PERIPH_BASE + TC0_ID) + #define INT_TC1 (INT_PERIPH_BASE + TC1_ID) + #define INT_TC2 (INT_PERIPH_BASE + TC2_ID) + #define INT_TC3 (INT_PERIPH_BASE + TC3_ID) + #define INT_TC4 (INT_PERIPH_BASE + TC4_ID) + #define INT_TC5 (INT_PERIPH_BASE + TC5_ID) + #define INT_ADC (INT_PERIPH_BASE + ADC_ID) + #define INT_DACC (INT_PERIPH_BASE + DACC_ID) + #define INT_PWM (INT_PERIPH_BASE + PWM_ID) + + // Total number of interrupts. + #define NUM_INTERRUPTS 48 + +#elif CPU_CM3_SAM3X + #define INT_SUPC (INT_PERIPH_BASE + SUPC_ID) + #define INT_RSTC (INT_PERIPH_BASE + RSTC_ID) + #define INT_RTC (INT_PERIPH_BASE + RTC_ID) + #define INT_RTT (INT_PERIPH_BASE + RTT_ID) + #define INT_WDT (INT_PERIPH_BASE + WDT_ID) + #define INT_PMC (INT_PERIPH_BASE + PMC_ID) + #define INT_EEFC0 (INT_PERIPH_BASE + EEFC0_ID) + #define INT_EEFC1 (INT_PERIPH_BASE + EEFC1_ID) + #define INT_UART0 (INT_PERIPH_BASE + UART0_ID) + #define INT_SMC_SDRAMC (INT_PERIPH_BASE + SMC_SDRAMC_ID) + #define INT_SDRAMC (INT_PERIPH_BASE + SDRAMC_ID) + #define INT_PIOA (INT_PERIPH_BASE + PIOA_ID) + #define INT_PIOB (INT_PERIPH_BASE + PIOB_ID) + #define INT_PIOC (INT_PERIPH_BASE + PIOC_ID) + #define INT_PIOD (INT_PERIPH_BASE + PIOD_ID) + #define INT_PIOE (INT_PERIPH_BASE + PIOE_ID) + #define INT_PIOF (INT_PERIPH_BASE + PIOF_ID) + #define INT_US0 (INT_PERIPH_BASE + US0_ID) + #define INT_US1 (INT_PERIPH_BASE + US1_ID) + #define INT_US2 (INT_PERIPH_BASE + US2_ID) + #define INT_US3 (INT_PERIPH_BASE + US3_ID) + #define INT_HSMCI (INT_PERIPH_BASE + HSMCI_ID) + #define INT_TWI0 (INT_PERIPH_BASE + TWI0_ID) + #define INT_TWI1 (INT_PERIPH_BASE + TWI1_ID) + #define INT_SPI0 (INT_PERIPH_BASE + SPI0_ID) + #define INT_SPI1 (INT_PERIPH_BASE + SPI1_ID) + #define INT_SSC (INT_PERIPH_BASE + SSC_ID) + #define INT_TC0 (INT_PERIPH_BASE + TC0_ID) + #define INT_TC1 (INT_PERIPH_BASE + TC1_ID) + #define INT_TC2 (INT_PERIPH_BASE + TC2_ID) + #define INT_TC3 (INT_PERIPH_BASE + TC3_ID) + #define INT_TC4 (INT_PERIPH_BASE + TC4_ID) + #define INT_TC5 (INT_PERIPH_BASE + TC5_ID) + #define INT_TC6 (INT_PERIPH_BASE + TC6_ID) + #define INT_TC7 (INT_PERIPH_BASE + TC7_ID) + #define INT_TC8 (INT_PERIPH_BASE + TC8_ID) + #define INT_PWM (INT_PERIPH_BASE + PWM_ID) + #define INT_ADC (INT_PERIPH_BASE + ADC_ID) + #define INT_DACC (INT_PERIPH_BASE + DACC_ID) + #define INT_DMAC (INT_PERIPH_BASE + DMAC_ID) + #define INT_UOTGHS (INT_PERIPH_BASE + UOTGHS_ID) + #define INT_TRNG (INT_PERIPH_BASE + TRNG_ID) + #define INT_EMAC (INT_PERIPH_BASE + EMAC_ID) + #define INT_CAN0 (INT_PERIPH_BASE + CAN0_ID) + #define INT_CAN1 (INT_PERIPH_BASE + CAN1_ID) + + // Total number of interrupts. + #define NUM_INTERRUPTS 61 + +#else + #error Peripheral IDs undefined +#endif /*\}*/ #endif /* SAM3_INTS_H */