X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fcortex-m3%2Fio%2Fsam3_smc.h;h=7f2faaa78e823248cffdde3de86f192e7cd08c83;hb=8d6571384018a22980c608e058f0d0d5b20b62b7;hp=ead911ccf97de24681098a0159a1cb705a73a3d3;hpb=956e3fe9e694127d180fab411806b9d96a5bd39a;p=bertos.git diff --git a/bertos/cpu/cortex-m3/io/sam3_smc.h b/bertos/cpu/cortex-m3/io/sam3_smc.h index ead911cc..7f2faaa7 100644 --- a/bertos/cpu/cortex-m3/io/sam3_smc.h +++ b/bertos/cpu/cortex-m3/io/sam3_smc.h @@ -36,9 +36,10 @@ #ifndef SAM3_SMC_H #define SAM3_SMC_H -#if !CPU_CM3_SAM3X && !CPU_CM3_SAM3U - #error SMC registers undefined for current cpu -#endif +/* + * SMC registers defined only for SAM3X/A and U for now + */ +#if CPU_CM3_SAM3X || CPU_CM3_SAM3U /** SMC registers base. */ #define SMC_BASE 0x400E0000 @@ -202,6 +203,100 @@ #define SMC_WPSR (*((reg32_t *)(SMC_BASE + SMC_WPSR_OFF))) /*\}*/ +/** + * NFC control addresses. + */ +/*\{*/ +#define NFC_SRAM_BASE_ADDR 0x20100000 ///< Base address of NFC SRAM +#define NFC_CMD_BASE_ADDR 0x60000000 ///< Base address for NFC Address Command +/*\}*/ + +/** + * NFC address command values. + */ +/*\{*/ +#define NFC_CMD_CMD1 (0xFF << 2) ///< Command Register Value for Cycle 1 +#define NFC_CMD_CMD2 (0xFF << 10) ///< Command Register Value for Cycle 2 +#define NFC_CMD_VCMD2 BV(18) ///< Valid Cycle 2 Command +#define NFC_CMD_ACYCLE_MASK (0x7 << 19) ///< Number of Address required for the current command +#define NFC_CMD_ACYCLE_NONE (0x0 << 19) ///< No address cycle +#define NFC_CMD_ACYCLE_ONE (0x1 << 19) ///< One address cycle +#define NFC_CMD_ACYCLE_TWO (0x2 << 19) ///< Two address cycles +#define NFC_CMD_ACYCLE_THREE (0x3 << 19) ///< Three address cycles +#define NFC_CMD_ACYCLE_FOUR (0x4 << 19) ///< Four address cycles +#define NFC_CMD_ACYCLE_FIVE (0x5 << 19) ///< Five address cycles +#define NFC_CMD_CSID_MASK (0x7 << 22) ///< Chip Select Identifier +#define NFC_CMD_CSID_0 (0x0 << 22) ///< CS0 +#define NFC_CMD_CSID_1 (0x1 << 22) ///< CS1 +#define NFC_CMD_CSID_2 (0x2 << 22) ///< CS2 +#define NFC_CMD_CSID_3 (0x3 << 22) ///< CS3 +#define NFC_CMD_CSID_4 (0x4 << 22) ///< CS4 +#define NFC_CMD_CSID_5 (0x5 << 22) ///< CS5 +#define NFC_CMD_CSID_6 (0x6 << 22) ///< CS6 +#define NFC_CMD_CSID_7 (0x7 << 22) ///< CS7 +#define NFC_CMD_NFCEN BV(25) ///< NFC Enable +#define NFC_CMD_NFCWR BV(26) ///< NFC Write Enable +#define NFC_CMD_NFCCMD BV(27) ///< NFC Command Enable +/*\}*/ + + +/** + * Defines for bit fields in SMC_CFG register. + */ +/*\{*/ +#define SMC_CFG_PAGESIZE_SHIFT 0 +#define SMC_CFG_PAGESIZE_MASK (0x3 << SMC_CFG_PAGESIZE_SHIFT) +#define SMC_CFG_PAGESIZE_PS512_16 (0x0 << 0) +#define SMC_CFG_PAGESIZE_PS1024_32 (0x1 << 0) +#define SMC_CFG_PAGESIZE_PS2048_64 (0x2 << 0) +#define SMC_CFG_PAGESIZE_PS4096_128 (0x3 << 0) +#define SMC_CFG_WSPARE (0x1 << 8) +#define SMC_CFG_RSPARE (0x1 << 9) +#define SMC_CFG_EDGECTRL (0x1 << 12) +#define SMC_CFG_RBEDGE (0x1 << 13) +#define SMC_CFG_DTOCYC_SHIFT 16 +#define SMC_CFG_DTOCYC_MASK (0xf << SMC_CFG_DTOCYC_SHIFT) +#define SMC_CFG_DTOCYC(value) (SMC_CFG_DTOCYC_MASK & ((value) << SMC_CFG_DTOCYC_SHIFT)) +#define SMC_CFG_DTOMUL_SHIFT 20 +#define SMC_CFG_DTOMUL_MASK (0x7 << SMC_CFG_DTOMUL_SHIFT) +#define SMC_CFG_DTOMUL_X1 (0x0 << 20) +#define SMC_CFG_DTOMUL_X16 (0x1 << 20) +#define SMC_CFG_DTOMUL_X128 (0x2 << 20) +#define SMC_CFG_DTOMUL_X256 (0x3 << 20) +#define SMC_CFG_DTOMUL_X1024 (0x4 << 20) +#define SMC_CFG_DTOMUL_X4096 (0x5 << 20) +#define SMC_CFG_DTOMUL_X65536 (0x6 << 20) +#define SMC_CFG_DTOMUL_X1048576 (0x7 << 20) +/*\}*/ + +/** + * Defines for bit fields in SMC_CTRL register. + */ +/*\{*/ +#define SMC_CTRL_NFCEN BV(0) +#define SMC_CTRL_NFCDIS BV(1) +/*\}*/ + +/** + * Defines for bit fields in SMC_SR register. + */ +/*\{*/ +#define SMC_SR_SMCSTS BV(0) +#define SMC_SR_RB_RISE BV(4) +#define SMC_SR_RB_FALL BV(5) +#define SMC_SR_NFCBUSY BV(8) +#define SMC_SR_NFCWR BV(11) +#define SMC_SR_NFCSID_SHIFT 12 +#define SMC_SR_NFCSID_MASK (0x7 << SMC_SR_NFCSID_SHIFT) +#define SMC_SR_XFRDONE BV(16) +#define SMC_SR_CMDDONE BV(17) +#define SMC_SR_DTOE BV(20) +#define SMC_SR_UNDEF BV(21) +#define SMC_SR_AWB BV(22) +#define SMC_SR_NFCASE BV(23) +#define SMC_SR_RB_EDGE0 BV(24) +/*\}*/ + /** * Defines for bit fields in SMC_SETUP registers. */ @@ -247,6 +342,32 @@ #define SMC_CYCLE_NRD_CYCLE(x) (SMC_CYCLE_NRD_CYCLE_MASK & ((x) << SMC_CYCLE_NRD_CYCLE_SHIFT)) /*\}*/ +/** + * Defines for bit fields in SMC_TIMINGS registers. + */ +/*\{*/ +#define SMC_TIMINGS_TCLR_SHIFT 0 +#define SMC_TIMINGS_TCLR_MASK (0xf << SMC_TIMINGS_TCLR_SHIFT) +#define SMC_TIMINGS_TCLR(value) (SMC_TIMINGS_TCLR_MASK & ((value) << SMC_TIMINGS_TCLR_SHIFT)) +#define SMC_TIMINGS_TADL_SHIFT 4 +#define SMC_TIMINGS_TADL_MASK (0xf << SMC_TIMINGS_TADL_SHIFT) +#define SMC_TIMINGS_TADL(value) (SMC_TIMINGS_TADL_MASK & ((value) << SMC_TIMINGS_TADL_SHIFT)) +#define SMC_TIMINGS_TAR_SHIFT 8 +#define SMC_TIMINGS_TAR_MASK (0xf << SMC_TIMINGS_TAR_SHIFT) +#define SMC_TIMINGS_TAR(value) (SMC_TIMINGS_TAR_MASK & ((value) << SMC_TIMINGS_TAR_SHIFT)) +#define SMC_TIMINGS_OCMS BV(12) +#define SMC_TIMINGS_TRR_SHIFT 16 +#define SMC_TIMINGS_TRR_MASK (0xf << SMC_TIMINGS_TRR_SHIFT) +#define SMC_TIMINGS_TRR(value) (SMC_TIMINGS_TRR_MASK & ((value) << SMC_TIMINGS_TRR_SHIFT)) +#define SMC_TIMINGS_TWB_SHIFT 24 +#define SMC_TIMINGS_TWB_MASK (0xf << SMC_TIMINGS_TWB_SHIFT) +#define SMC_TIMINGS_TWB(value) (SMC_TIMINGS_TWB_MASK & ((value) << SMC_TIMINGS_TWB_SHIFT)) +#define SMC_TIMINGS_RBNSEL_SHIFT 28 +#define SMC_TIMINGS_RBNSEL_MASK (0x7 << SMC_TIMINGS_RBNSEL_SHIFT) +#define SMC_TIMINGS_RBNSEL(value) (SMC_TIMINGS_RBNSEL_MASK & ((value) << SMC_TIMINGS_RBNSEL_SHIFT)) +#define SMC_TIMINGS_NFSEL BV(31) +/*\}*/ + /** * Defines for bit fields in SMC_MODE registers. */ @@ -266,4 +387,6 @@ #define SMC_MODE_TDF_MODE BV(20) /*\}*/ +#endif /* CPU_CM3_SAM3X || CPU_CM3_SAM3U */ + #endif /* SAM3_SMC_H */