X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fcortex-m3%2Fio%2Fsam3_smc.h;h=8998d8364e2801a5376d6f9b25cbed3f4777d912;hb=f9344771c58957fe73566e97cffcab3c8acafacc;hp=7f2faaa78e823248cffdde3de86f192e7cd08c83;hpb=8d6571384018a22980c608e058f0d0d5b20b62b7;p=bertos.git diff --git a/bertos/cpu/cortex-m3/io/sam3_smc.h b/bertos/cpu/cortex-m3/io/sam3_smc.h index 7f2faaa7..8998d836 100644 --- a/bertos/cpu/cortex-m3/io/sam3_smc.h +++ b/bertos/cpu/cortex-m3/io/sam3_smc.h @@ -218,6 +218,7 @@ #define NFC_CMD_CMD1 (0xFF << 2) ///< Command Register Value for Cycle 1 #define NFC_CMD_CMD2 (0xFF << 10) ///< Command Register Value for Cycle 2 #define NFC_CMD_VCMD2 BV(18) ///< Valid Cycle 2 Command +#define NFC_CMD_ACYCLE_SHIFT 19 #define NFC_CMD_ACYCLE_MASK (0x7 << 19) ///< Number of Address required for the current command #define NFC_CMD_ACYCLE_NONE (0x0 << 19) ///< No address cycle #define NFC_CMD_ACYCLE_ONE (0x1 << 19) ///< One address cycle @@ -225,15 +226,8 @@ #define NFC_CMD_ACYCLE_THREE (0x3 << 19) ///< Three address cycles #define NFC_CMD_ACYCLE_FOUR (0x4 << 19) ///< Four address cycles #define NFC_CMD_ACYCLE_FIVE (0x5 << 19) ///< Five address cycles -#define NFC_CMD_CSID_MASK (0x7 << 22) ///< Chip Select Identifier -#define NFC_CMD_CSID_0 (0x0 << 22) ///< CS0 -#define NFC_CMD_CSID_1 (0x1 << 22) ///< CS1 -#define NFC_CMD_CSID_2 (0x2 << 22) ///< CS2 -#define NFC_CMD_CSID_3 (0x3 << 22) ///< CS3 -#define NFC_CMD_CSID_4 (0x4 << 22) ///< CS4 -#define NFC_CMD_CSID_5 (0x5 << 22) ///< CS5 -#define NFC_CMD_CSID_6 (0x6 << 22) ///< CS6 -#define NFC_CMD_CSID_7 (0x7 << 22) ///< CS7 +#define NFC_CMD_CSID_SHIFT 22 ///< Chip Select shift +#define NFC_CMD_CSID_MASK (0x7 << NFC_CMD_CSID_SHIFT) ///< Chip Select mask #define NFC_CMD_NFCEN BV(25) ///< NFC Enable #define NFC_CMD_NFCWR BV(26) ///< NFC Write Enable #define NFC_CMD_NFCCMD BV(27) ///< NFC Command Enable @@ -297,6 +291,31 @@ #define SMC_SR_RB_EDGE0 BV(24) /*\}*/ +/** + * Defines for bit fields in SMC_ECC_CTRL register + */ +/*\{*/ +#define SMC_ECC_CTRL_RST BV(0) +#define SMC_ECC_CTRL_SWRST BV(1) +/*\}*/ + +/** + * Defines for bit fields in SMC_ECC_MD register + */ +/*\{*/ +#define SMC_ECC_MD_ECC_PAGESIZE_SHIFT 0 +#define SMC_ECC_MD_ECC_PAGESIZE_MASK 0x3 +#define SMC_ECC_MD_ECC_PAGESIZE_PS512_16 0x0 +#define SMC_ECC_MD_ECC_PAGESIZE_PS1024_32 0x1 +#define SMC_ECC_MD_ECC_PAGESIZE_PS2048_64 0x2 +#define SMC_ECC_MD_ECC_PAGESIZE_PS4096_128 0x3 +#define SMC_ECC_MD_TYPCORREC_SHIFT 4 +#define SMC_ECC_MD_TYPCORREC_MASK (0x3 << SMC_ECC_MD_TYPCORREC_SHIFT) +#define SMC_ECC_MD_TYPCORREC_CPAGE (0x0 << SMC_ECC_MD_TYPCORREC_SHIFT) +#define SMC_ECC_MD_TYPCORREC_C256B (0x1 << SMC_ECC_MD_TYPCORREC_SHIFT) +#define SMC_ECC_MD_TYPCORREC_C512B (0x2 << SMC_ECC_MD_TYPCORREC_SHIFT) +/*\}*/ + /** * Defines for bit fields in SMC_SETUP registers. */