X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fcortex-m3%2Fio%2Fsam3_sysctl.h;h=f83cce2185cc6dcd1577c27b02a6477755bfcd9b;hb=a3ffb42b8a665abcbc54d8cfd290c368ab5f083c;hp=4be512925e25ac5f4ad3bb5322294f6c6fcfacd0;hpb=78fdf752f2518b86d94e69f6d099b3e43aca35eb;p=bertos.git diff --git a/bertos/cpu/cortex-m3/io/sam3_sysctl.h b/bertos/cpu/cortex-m3/io/sam3_sysctl.h index 4be51292..f83cce21 100644 --- a/bertos/cpu/cortex-m3/io/sam3_sysctl.h +++ b/bertos/cpu/cortex-m3/io/sam3_sysctl.h @@ -30,73 +30,77 @@ * * --> * - * \brief ATSAM3 system controller registers. + * \brief Atmel SAM3 system controller registers. */ #ifndef SAM3_SYSCTL_H #define SAM3_SYSCTL_H +/** Supply controller base */ +#define SUPC_BASE 0x400E1410 + /** - * Supply controller registers. + * Supply controller offsets. */ /*\{*/ -#define SUPC_CR_R (*((reg32_t *)0x400E1410)) ///< Supply Controller Control -#define SUPC_SMMR_R (*((reg32_t *)0x400E1414)) ///< Supply Controller Supply Monitor Mode -#define SUPC_MR_R (*((reg32_t *)0x400E1418)) ///< Supply Controller Mode -#define SUPC_WUMR_R (*((reg32_t *)0x400E141C)) ///< Supply Controller Wake Up Mode -#define SUPC_WUIR_R (*((reg32_t *)0x400E1420)) ///< Supply Controller Wake Up Inputs -#define SUPC_SR_R (*((reg32_t *)0x400E1424)) ///< Supply Controller Status +#define SUPC_CR_OFF 0x0 ///< Supply Controller Control +#define SUPC_SMMR_OFF 0x4 ///< Supply Controller Supply Monitor Mode +#define SUPC_MR_OFF 0x8 ///< Supply Controller Mode +#define SUPC_WUMR_OFF 0xC ///< Supply Controller Wake Up Mode +#define SUPC_WUIR_OFF 0x10 ///< Supply Controller Wake Up Inputs +#define SUPC_SR_OFF 0x14 ///< Supply Controller Status /*\}*/ /** - * Supply controller addresses. + * Supply controller registers. */ /*\{*/ -#define SUPC_CR 0x400E1410 ///< Supply Controller Control -#define SUPC_SMMR 0x400E1414 ///< Supply Controller Supply Monitor Mode -#define SUPC_MR 0x400E1418 ///< Supply Controller Mode -#define SUPC_WUMR 0x400E141C ///< Supply Controller Wake Up Mode -#define SUPC_WUIR 0x400E1420 ///< Supply Controller Wake Up Inputs #define SUPC_SR 0x400E1424 ///< Supply Controller Status +#define SUPC_CR (*((reg32_t *)(SUPC_BASE + SUPC_CR_OFF ))) ///< Supply Controller Control +#define SUPC_SMMR (*((reg32_t *)(SUPC_BASE + SUPC_SMMR_OFF))) ///< Supply Controller Supply Monitor Mode +#define SUPC_MR (*((reg32_t *)(SUPC_BASE + SUPC_MR_OFF ))) ///< Supply Controller Mode +#define SUPC_WUMR (*((reg32_t *)(SUPC_BASE + SUPC_WUMR_OFF))) ///< Supply Controller Wake Up Mode +#define SUPC_WUIR (*((reg32_t *)(SUPC_BASE + SUPC_WUIR_OFF))) ///< Supply Controller Wake Up Inputs +#define SUPC_SR (*((reg32_t *)(SUPC_BASE + SUPC_SR_OFF ))) ///< Supply Controller Status /*\}*/ /** * Defines for bit fields in SUPC_CR register. */ /*\{*/ -#define SUPC_CR_VROFF BV(2) ///< Voltage Regulator Off -#define SUPC_CR_XTALSEL BV(3) ///< Crystal Oscillator Select +#define SUPC_CR_VROFF 2 ///< Voltage Regulator Off +#define SUPC_CR_XTALSEL 3 ///< Crystal Oscillator Select #define SUPC_CR_KEY_P 24 -#define SUPC_CR_KEY_M (0xff << SUPC_CR_KEY_P) ///< SUPC_CR key -#define SUPC_CR_KEY(value) (SUPC_CR_KEY_M & ((value) << SUPC_CR_KEY_P)) +#define SUPC_CR_KEY_MASK (0xff << SUPC_CR_KEY_P) ///< SUPC_CR key +#define SUPC_CR_KEY(value) (SUPC_CR_KEY_MASK & ((value) << SUPC_CR_KEY_P)) /*\}*/ /** * Defines for bit fields in SUPC_SR register. */ /*\{*/ -#define SUPC_SR_WKUPS BV(1) ///< WKUP Wake Up Status -#define SUPC_SR_SMWS BV(2) ///< Supply Monitor Detection Wake Up Status -#define SUPC_SR_BODRSTS BV(3) ///< Brownout Detector Reset Status -#define SUPC_SR_SMRSTS BV(4) ///< Supply Monitor Reset Status -#define SUPC_SR_SMS BV(5) ///< Supply Monitor Status -#define SUPC_SR_SMOS BV(6) ///< Supply Monitor Output Status -#define SUPC_SR_OSCSEL BV(7) ///< 32-kHz Oscillator Selection Status -#define SUPC_SR_WKUPIS0 BV(16) ///< WKUP Input Status 0 -#define SUPC_SR_WKUPIS1 BV(17) ///< WKUP Input Status 1 -#define SUPC_SR_WKUPIS2 BV(18) ///< WKUP Input Status 2 -#define SUPC_SR_WKUPIS3 BV(19) ///< WKUP Input Status 3 -#define SUPC_SR_WKUPIS4 BV(20) ///< WKUP Input Status 4 -#define SUPC_SR_WKUPIS5 BV(21) ///< WKUP Input Status 5 -#define SUPC_SR_WKUPIS6 BV(22) ///< WKUP Input Status 6 -#define SUPC_SR_WKUPIS7 BV(23) ///< WKUP Input Status 7 -#define SUPC_SR_WKUPIS8 BV(24) ///< WKUP Input Status 8 -#define SUPC_SR_WKUPIS9 BV(25) ///< WKUP Input Status 9 -#define SUPC_SR_WKUPIS10 BV(26) ///< WKUP Input Status 10 -#define SUPC_SR_WKUPIS11 BV(27) ///< WKUP Input Status 11 -#define SUPC_SR_WKUPIS12 BV(28) ///< WKUP Input Status 12 -#define SUPC_SR_WKUPIS13 BV(29) ///< WKUP Input Status 13 -#define SUPC_SR_WKUPIS14 BV(30) ///< WKUP Input Status 14 -#define SUPC_SR_WKUPIS15 BV(31) ///< WKUP Input Status 15 +#define SUPC_SR_WKUPS 1 ///< WKUP Wake Up Status +#define SUPC_SR_SMWS 2 ///< Supply Monitor Detection Wake Up Status +#define SUPC_SR_BODRSTS 3 ///< Brownout Detector Reset Status +#define SUPC_SR_SMRSTS 4 ///< Supply Monitor Reset Status +#define SUPC_SR_SMS 5 ///< Supply Monitor Status +#define SUPC_SR_SMOS 6 ///< Supply Monitor Output Status +#define SUPC_SR_OSCSEL 7 ///< 32-kHz Oscillator Selection Status +#define SUPC_SR_WKUPIS0 16 ///< WKUP Input Status 0 +#define SUPC_SR_WKUPIS1 17 ///< WKUP Input Status 1 +#define SUPC_SR_WKUPIS2 18 ///< WKUP Input Status 2 +#define SUPC_SR_WKUPIS3 19 ///< WKUP Input Status 3 +#define SUPC_SR_WKUPIS4 20 ///< WKUP Input Status 4 +#define SUPC_SR_WKUPIS5 21 ///< WKUP Input Status 5 +#define SUPC_SR_WKUPIS6 22 ///< WKUP Input Status 6 +#define SUPC_SR_WKUPIS7 23 ///< WKUP Input Status 7 +#define SUPC_SR_WKUPIS8 24 ///< WKUP Input Status 8 +#define SUPC_SR_WKUPIS9 25 ///< WKUP Input Status 9 +#define SUPC_SR_WKUPIS10 26 ///< WKUP Input Status 10 +#define SUPC_SR_WKUPIS11 27 ///< WKUP Input Status 11 +#define SUPC_SR_WKUPIS12 28 ///< WKUP Input Status 12 +#define SUPC_SR_WKUPIS13 29 ///< WKUP Input Status 13 +#define SUPC_SR_WKUPIS14 30 ///< WKUP Input Status 14 +#define SUPC_SR_WKUPIS15 31 ///< WKUP Input Status 15 /*\}*/ #endif /* SAM3_SYSCTL_H */