X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fcortex-m3%2Fio%2Fstm32_adc.h;h=d81843ee385248e178ded35d3bf410d722164bea;hb=a0ba2de64a3964445b392a269ac820c03c5b8385;hp=b884b5265630fce6c8e5f467455f21a58c226f62;hpb=c035fbd2061de9ff531e902ba4cc4e84cb662fc9;p=bertos.git diff --git a/bertos/cpu/cortex-m3/io/stm32_adc.h b/bertos/cpu/cortex-m3/io/stm32_adc.h index b884b526..d81843ee 100644 --- a/bertos/cpu/cortex-m3/io/stm32_adc.h +++ b/bertos/cpu/cortex-m3/io/stm32_adc.h @@ -81,8 +81,8 @@ #define ADC_CHANNEL_13 ((uint8_t)0x0D) #define ADC_CHANNEL_14 ((uint8_t)0x0E) #define ADC_CHANNEL_15 ((uint8_t)0x0F) -#define ADC_CHANNEL_16 ((uint8_t)0X10) -#define ADC_CHANNEL_17 ((uint8_t)0X11) +#define ADC_CHANNEL_16 ((uint8_t)0x10) +#define ADC_CHANNEL_17 ((uint8_t)0x11) /* ADC sampling times */ #define ADC_SAMPLETIME_1CYCLES5 ((uint8_t)0x00) @@ -132,89 +132,89 @@ #define ADC_FLAG_STRT ((uint8_t)0X10) -/* ADC ADON mask */ -#define CR2_ADON_SET ((uint32_t)0x00000001) -#define CR2_ADON_RESET ((uint32_t)0xFFFFFFFE) - -/* ADC DMA mask */ -#define CR2_DMA_SET ((uint16_t)0x0100) -#define CR2_DMA_RESET ((uint16_t)0xFEFF) - -/* ADC RSTCAL mask */ -#define CR2_RSTCAL_SET ((uint16_t)0x0008) - -/* ADC CAL mask */ -#define CR2_CAL_SET ((uint16_t)0x0004) - -/* ADC SWSTRT mask */ -#define CR2_SWSTRT_SET ((uint32_t)0x00400000) - -/* ADC DISCNUM mask */ -#define CR1_DISCNUM_RESET ((uint32_t)0xFFFF1FFF) - -/* ADC DISCEN mask */ -#define CR1_DISCEN_SET ((uint32_t)0x00000800) -#define CR1_DISCEN_RESET ((uint32_t)0xFFFFF7FF) - -/* ADC EXTTRIG mask */ -#define CR2_EXTTRIG_SET ((uint32_t)0x00100000) -#define CR2_EXTTRIG_RESET ((uint32_t)0xFFEFFFFF) - -/* ADC Software start mask */ -#define CR2_EXTTRIG_SWSTRT_SET ((uint32_t)0x00500000) -#define CR2_EXTTRIG_SWSTRT_RESET ((uint32_t)0xFFAFFFFF) - -/* ADC JAUTO mask */ -#define CR1_JAUTO_SET ((uint32_t)0x00000400) -#define CR1_JAUTO_RESET ((uint32_t)0xFFFFFBFF) - -/* ADC JDISCEN mask */ -#define CR1_JDISCEN_SET ((uint32_t)0x00001000) -#define CR1_JDISCEN_RESET ((uint32_t)0xFFFFEFFF) - -/* ADC JEXTSEL mask */ -#define CR2_JEXTSEL_RESET ((uint32_t)0xFFFF8FFF) - -/* ADC JEXTTRIG mask */ -#define CR2_JEXTTRIG_SET ((uint32_t)0x00008000) -#define CR2_JEXTTRIG_RESET ((uint32_t)0xFFFF7FFF) - -/* ADC JSWSTRT mask */ -#define CR2_JSWSTRT_SET ((uint32_t)0x00200000) - -/* ADC injected software start mask */ -#define CR2_JEXTTRIG_JSWSTRT_SET ((uint32_t)0x00208000) -#define CR2_JEXTTRIG_JSWSTRT_RESET ((uint32_t)0xFFDF7FFF) - -/* ADC AWDCH mask */ -#define CR1_AWDCH_RESET ((uint32_t)0xFFFFFFE0) - -/* ADC SQx mask */ -#define SQR3_SQ_MASK ((uint8_t)0x1F) -#define SQR2_SQ_MASK ((uint8_t)0x1F) +/* ADC ADON mask */ +#define CR2_ADON_SET ((uint32_t)0x00000001) +#define CR2_ADON_RESET ((uint32_t)0xFFFFFFFE) + +/* ADC DMA mask */ +#define CR2_DMA_SET ((uint16_t)0x0100) +#define CR2_DMA_RESET ((uint16_t)0xFEFF) + +/* ADC RSTCAL mask */ +#define CR2_RSTCAL_SET ((uint16_t)0x0008) + +/* ADC CAL mask */ +#define CR2_CAL_SET ((uint16_t)0x0004) + +/* ADC SWSTRT mask */ +#define CR2_SWSTRT_SET ((uint32_t)0x00400000) + +/* ADC DISCNUM mask */ +#define CR1_DISCNUM_RESET ((uint32_t)0xFFFF1FFF) + +/* ADC DISCEN mask */ +#define CR1_DISCEN_SET ((uint32_t)0x00000800) +#define CR1_DISCEN_RESET ((uint32_t)0xFFFFF7FF) + +/* ADC EXTTRIG mask */ +#define CR2_EXTTRIG_SET ((uint32_t)0x00100000) +#define CR2_EXTTRIG_RESET ((uint32_t)0xFFEFFFFF) + +/* ADC Software start mask */ +#define CR2_EXTTRIG_SWSTRT_SET ((uint32_t)0x00500000) +#define CR2_EXTTRIG_SWSTRT_RESET ((uint32_t)0xFFAFFFFF) + +/* ADC JAUTO mask */ +#define CR1_JAUTO_SET ((uint32_t)0x00000400) +#define CR1_JAUTO_RESET ((uint32_t)0xFFFFFBFF) + +/* ADC JDISCEN mask */ +#define CR1_JDISCEN_SET ((uint32_t)0x00001000) +#define CR1_JDISCEN_RESET ((uint32_t)0xFFFFEFFF) + +/* ADC JEXTSEL mask */ +#define CR2_JEXTSEL_RESET ((uint32_t)0xFFFF8FFF) + +/* ADC JEXTTRIG mask */ +#define CR2_JEXTTRIG_SET ((uint32_t)0x00008000) +#define CR2_JEXTTRIG_RESET ((uint32_t)0xFFFF7FFF) + +/* ADC JSWSTRT mask */ +#define CR2_JSWSTRT_SET ((uint32_t)0x00200000) + +/* ADC injected software start mask */ +#define CR2_JEXTTRIG_JSWSTRT_SET ((uint32_t)0x00208000) +#define CR2_JEXTTRIG_JSWSTRT_RESET ((uint32_t)0xFFDF7FFF) + +/* ADC AWDCH mask */ +#define CR1_AWDCH_RESET ((uint32_t)0xFFFFFFE0) + +/* ADC SQx mask */ +#define SQR3_SQ_MASK ((uint8_t)0x1F) +#define SQR2_SQ_MASK ((uint8_t)0x1F) #define SQR1_SQ_MASK ((uint8_t)0x1F) #define SQR1_SQ_LEN_MASK 0xF -#define SQR1_SQ_LEN_SHIFT 20 - -/* ADC JSQx mask */ -#define JSQR_JSQ_SET ((uint8_t)0x1F) - -/* ADC JL mask */ -#define JSQR_JL_RESET ((uint32_t)0xFFCFFFFF) - -/* ADC SMPx mask */ -#define SMPR1_SMP_SET ((uint8_t)0x07) -#define SMPR2_SMP_SET ((uint8_t)0x07) - -/* ADC Analog watchdog enable mode mask */ -#define CR1_AWDMODE_RESET ((uint32_t)0xFF3FFDFF) - -/* ADC TSPD mask */ -#define CR2_TSVREFE_SET ((uint32_t)0x00800000) -#define CR2_TSVREFE_RESET ((uint32_t)0xFF7FFFFF) - -/* ADC JDRx registers= offset */ -#define JDR_OFFSET ((uint8_t)0x28) +#define SQR1_SQ_LEN_SHIFT 20 + +/* ADC JSQx mask */ +#define JSQR_JSQ_SET ((uint8_t)0x1F) + +/* ADC JL mask */ +#define JSQR_JL_RESET ((uint32_t)0xFFCFFFFF) + +/* ADC SMPx mask */ +#define SMPR1_SMP_SET ((uint8_t)0x07) +#define SMPR2_SMP_SET ((uint8_t)0x07) + +/* ADC Analog watchdog enable mode mask */ +#define CR1_AWDMODE_RESET ((uint32_t)0xFF3FFDFF) + +/* ADC TSPD mask */ +#define CR2_TSVREFE_SET ((uint32_t)0x00800000) +#define CR2_TSVREFE_RESET ((uint32_t)0xFF7FFFFF) + +/* ADC JDRx registers= offset */ +#define JDR_OFFSET ((uint8_t)0x28) /* ADC CR1 register */ #define CR1_EOCIE 5 @@ -247,12 +247,42 @@ #define SR_JEOC 2 #define SR_JSTRT 3 #define SR_STRT 4 - -/* ADC registers Masks */ -#define CR1_ADC_CLEAR_MASK ((uint32_t)0xFFF0FEFF) -#define CR2_ADC_CLEAR_MASK ((uint32_t)0xFFF1F7FD) -#define SQR1_CLEAR_MASK ((uint32_t)0xFF0FFFFF) - + +/* ADC sample time */ +#define SMPR1_CH17 21 +#define SMPR1_CH16 18 +#define SMPR1_CH15 15 +#define SMPR1_CH14 12 +#define SMPR1_CH13 9 +#define SMPR1_CH12 6 +#define SMPR1_CH11 3 +#define SMPR1_CH10 0 + +#define SMPR2_CH9 27 +#define SMPR2_CH8 24 +#define SMPR2_CH7 21 +#define SMPR2_CH6 18 +#define SMPR2_CH5 15 +#define SMPR2_CH4 12 +#define SMPR2_CH3 9 +#define SMPR2_CH2 6 +#define SMPR2_CH1 3 +#define SMPR2_CH0 0 + +/* ADC registers Masks */ +#define CR1_ADC_CLEAR_MASK ((uint32_t)0xFFF0FEFF) +#define CR2_ADC_CLEAR_MASK ((uint32_t)0xFFF1F7FD) +#define SQR1_CLEAR_MASK ((uint32_t)0xFF0FFFFF) + + + +/* ADC defines for SMT32F103Bxx */ +#define ADC_TEMP_V25 4300 // uV / C +#define ADC_TEMP_SLOPE 1430 // mV +#define ADC_TEMP_CONST 25000 +#define ADC_TEMP_CH 16 +#define ADC_VREFINT_CH 17 + struct stm32_adc { reg32_t SR;