X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fcortex-m3%2Fio%2Fstm32_uart.h;h=e35fc4475256ddd79feaf0db675ade07964fe0ae;hb=a0ba2de64a3964445b392a269ac820c03c5b8385;hp=13e31cde10527ad9347b449124e7afd9a1752cb0;hpb=498cdb373c387a72391fb04a7279d211391b3d39;p=bertos.git

diff --git a/bertos/cpu/cortex-m3/io/stm32_uart.h b/bertos/cpu/cortex-m3/io/stm32_uart.h
index 13e31cde..e35fc447 100644
--- a/bertos/cpu/cortex-m3/io/stm32_uart.h
+++ b/bertos/cpu/cortex-m3/io/stm32_uart.h
@@ -138,7 +138,7 @@
 #define CR1_RWU_SET               ((uint16_t)0x0002)  /* USART mute mode Enable MASK */
 #define CR1_RWU_RESET             ((uint16_t)0xFFFD)  /* USART mute mode Enable MASK */
 #define CR1_SBK_SET               ((uint16_t)0x0001)  /* USART Break Character send MASK */
-#define CR1_CLEAR_MASK            ((uint16_t)0xE9F3)  /* USART CR1 MASK */
+#define CR1_USART_CLEAR_MASK      ((uint16_t)0xE9F3)  /* USART CR1 MASK */
 #define CR1_UE                                   13
 #define CR1_M                                    12
 #define CR1_WAKE                                 11
@@ -157,7 +157,7 @@
 #define CR2_MASK                  ((uint16_t)0xFFF0)  /* USART address MASK */
 #define CR2_LINE_SET              ((uint16_t)0x4000)  /* USART LIN Enable MASK */
 #define CR2_LINE_RESET            ((uint16_t)0xBFFF)  /* USART LIN Disable MASK */
-#define CR2_CLEAR_MASK            ((uint16_t)0xC0FF)  /* USART CR2 MASK */
+#define CR2_USART_CLEAR_MASK      ((uint16_t)0xC0FF)  /* USART CR2 MASK */
 
 #define CR3_SCEN_SET              ((uint16_t)0x0020)  /* USART SC Enable MASK */
 #define CR3_SCEN_RESET            ((uint16_t)0xFFDF)  /* USART SC Disable MASK */
@@ -172,6 +172,19 @@
 #define CR3_IREN_RESET            ((uint16_t)0xFFFD)  /* USART IrDA Disable MASK */
 #define CR3_CLEAR_MASK            ((uint16_t)0xFCFF)  /* USART CR3 MASK */
 
+
+/* Status */
+#define SR_CTS                                    9
+#define SR_LBD                                    8
+#define SR_TXE                                    7
+#define SR_TC                                     6
+#define SR_RXNE                                   5
+#define SR_IDLE                                   4
+#define SR_ORE                                    3
+#define SR_NE                                     2
+#define SR_FE                                     1
+#define SR_PE                                     0
+
 #define GTPR_LSB_MASK             ((uint16_t)0x00FF)  /* Guard Time Register LSB MASK */
 #define GTPR_MSB_MASK             ((uint16_t)0xFF00)  /* Guard Time Register MSB MASK */