X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fdetect.h;h=41b190f5b769fdd443c6eb98d14b6ee77768e45a;hb=0a06817da12212b29cac740066fe51c89e1084af;hp=1ece26e5046b499de7b8af16ffe8c94908405be3;hpb=78c2d08d43a58d8579fd3993b1798b82b39a3703;p=bertos.git diff --git a/bertos/cpu/detect.h b/bertos/cpu/detect.h index 1ece26e5..41b190f5 100644 --- a/bertos/cpu/detect.h +++ b/bertos/cpu/detect.h @@ -40,7 +40,7 @@ || defined(__ARM4TM__) /* IAR: defined for all cores >= 4tm */ #define CPU_ARM 1 #define CPU_ID arm - #define CPU_CORE_NAME "ARM7TDMI" + #define CPU_CORE_NAME "ARM7TDMI" // AT91SAM7S core family #if defined(__ARM_AT91SAM7S32__) @@ -205,6 +205,14 @@ #define CPU_CM3_LM3S8962 0 #endif + #if defined (__ARM_STM32F101C4__) + #define CPU_CM3_STM32 1 + #define CPU_CM3_STM32F101C4 1 + #define CPU_NAME "STM32F101C4" + #else + #define CPU_CM3_STM32F101C4 0 + #endif + #if defined (__ARM_STM32F103RB__) #define CPU_CM3_STM32 1 #define CPU_CM3_STM32F103RB 1 @@ -213,40 +221,58 @@ #define CPU_CM3_STM32F103RB 0 #endif - #if defined (__ARM_AT91SAM3N4__) - #define CPU_CM3_AT91SAM3 1 - #define CPU_CM3_AT91SAM3N 1 - #define CPU_CM3_AT91SAM3N4 1 - #define CPU_NAME "AT91SAM3N4" + #if defined (__ARM_SAM3N4__) + #define CPU_CM3_SAM3 1 + #define CPU_CM3_SAM3N 1 + #define CPU_CM3_SAM3N4 1 + #define CPU_NAME "SAM3N4" + + #define CPU_CM3_SAM3S 0 + #define CPU_CM3_SAM3U 0 + #define CPU_CM3_SAM3N2 0 + #define CPU_CM3_SAM3N1 0 + #define CPU_CM3_SAM3X 0 + #else + #define CPU_CM3_SAM3N4 0 + #endif + + #if defined (__ARM_SAM3S4__) + #define CPU_CM3_SAM3 1 + #define CPU_CM3_SAM3S 1 + #define CPU_CM3_SAM3S4 1 + #define CPU_NAME "SAM3S4" - #define CPU_CM3_AT91SAM3S 0 - #define CPU_CM3_AT91SAM3U 0 + #define CPU_CM3_SAM3N 0 + #define CPU_CM3_SAM3U 0 + #define CPU_CM3_SAM3X 0 #else - #define CPU_CM3_AT91SAM3N4 0 + #define CPU_CM3_SAM3S4 0 #endif - #if defined (__ARM_AT91SAM3S4__) - #define CPU_CM3_AT91SAM3 1 - #define CPU_CM3_AT91SAM3S 1 - #define CPU_CM3_AT91SAM3S4 1 - #define CPU_NAME "AT91SAM3S4" + #if defined (__ARM_SAM3U4__) + #define CPU_CM3_SAM3 1 + #define CPU_CM3_SAM3U 1 + #define CPU_CM3_SAM3U4 1 + #define CPU_NAME "SAM3U4" - #define CPU_CM3_AT91SAM3N 0 - #define CPU_CM3_AT91SAM3U 0 + #define CPU_CM3_SAM3N 0 + #define CPU_CM3_SAM3S 0 + #define CPU_CM3_SAM3X 0 #else - #define CPU_CM3_AT91SAM3S4 0 + #define CPU_CM3_SAM3U4 0 #endif - #if defined (__ARM_AT91SAM3U4__) - #define CPU_CM3_AT91SAM3 1 - #define CPU_CM3_AT91SAM3U 1 - #define CPU_CM3_AT91SAM3U4 1 - #define CPU_NAME "AT91SAM3U4" + #if defined (__ARM_SAM3X8__) + #define CPU_CM3_SAM3 1 + #define CPU_CM3_SAM3X 1 + #define CPU_CM3_SAM3X8 1 + #define CPU_NAME "SAM3X8" - #define CPU_CM3_AT91SAM3N 0 - #define CPU_CM3_AT91SAM3S 0 + #define CPU_CM3_SAM3N 0 + #define CPU_CM3_SAM3S 0 + #define CPU_CM3_SAM3U 0 #else - #define CPU_CM3_AT91SAM3U4 0 + #define CPU_CM3_SAM3X8 0 #endif #if defined (CPU_CM3_LM3S) @@ -254,19 +280,19 @@ #error Luminary Cortex-M3 CPU configuration error #endif #define CPU_CM3_STM32 0 - #define CPU_CM3_AT91SAM3 0 + #define CPU_CM3_SAM3 0 #elif defined (CPU_CM3_STM32) - #if CPU_CM3_STM32F103RB + 0 != 1 + #if CPU_CM3_STM32F101C4 + CPU_CM3_STM32F103RB + 0 != 1 #error STM32 Cortex-M3 CPU configuration error #endif #define CPU_CM3_LM3S 0 - #define CPU_CM3_AT91SAM3 0 - #elif defined (CPU_CM3_AT91SAM3) - #if CPU_CM3_AT91SAM3N + 0 != 1 - #error AT91SAM3 Cortex-M3 CPU configuration error + #define CPU_CM3_SAM3 0 + #elif defined (CPU_CM3_SAM3) + #if CPU_CM3_SAM3N + CPU_CM3_SAM3U + CPU_CM3_SAM3S + CPU_CM3_SAM3X + 0 != 1 + #error SAM3 Cortex-M3 CPU configuration error #endif - #if CPU_CM3_AT91SAM3N4 + CPU_CM3_AT91SAM3S4 + CPU_CM3_AT91SAM3U4 + 0 != 1 - #error AT91SAM3 Cortex-M3 CPU configuration error + #if CPU_CM3_SAM3N4 + CPU_CM3_SAM3S4 + CPU_CM3_SAM3U4 + CPU_CM3_SAM3X8 + 0 != 1 + #error SAM3 Cortex-M3 CPU configuration error #endif #define CPU_CM3_LM3S 0 #define CPU_CM3_STM32 0 @@ -274,11 +300,11 @@ #else #define CPU_CM3_LM3S 0 #define CPU_CM3_STM32 0 - #define CPU_CM3_AT91SAM3 0 + #define CPU_CM3_SAM3 0 #endif - #if CPU_CM3_LM3S + CPU_CM3_STM32 + CPU_CM3_AT91SAM3 + 0 /* Add other Cortex-M3 families here */ != 1 + #if CPU_CM3_LM3S + CPU_CM3_STM32 + CPU_CM3_SAM3 + 0 /* Add other Cortex-M3 families here */ != 1 #error Cortex-M3 CPU configuration error #endif @@ -290,10 +316,13 @@ #define CPU_CM3_STM32 0 #define CPU_CM3_STM32F103RB 0 + #define CPU_CM3_STM32F101C4 0 - #define CPU_CM3_AT91SAM3 0 - #define CPU_CM3_AT91SAM3N 0 - #define CPU_CM3_AT91SAM3N4 0 + #define CPU_CM3_SAM3 0 + #define CPU_CM3_SAM3N 0 + #define CPU_CM3_SAM3N4 0 + #define CPU_CM3_SAM3X 0 + #define CPU_CM3_SAM3X8 0 #endif #if (defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC)) \ @@ -421,9 +450,16 @@ #define CPU_AVR_ATMEGA1280 0 #endif + #if defined(__AVR_ATmega2560__) + #define CPU_AVR_ATMEGA2560 1 + #define CPU_NAME "ATmega2560" + #else + #define CPU_AVR_ATMEGA2560 0 + #endif + #if CPU_AVR_ATMEGA32 + CPU_AVR_ATMEGA64 + CPU_AVR_ATMEGA103 + CPU_AVR_ATMEGA128 \ + CPU_AVR_ATMEGA8 + CPU_AVR_ATMEGA168 + CPU_AVR_ATMEGA328P + CPU_AVR_ATMEGA1281 \ - + CPU_AVR_ATMEGA1280 != 1 + + CPU_AVR_ATMEGA1280 + CPU_AVR_ATMEGA2560 != 1 #error AVR CPU configuration error #endif #else @@ -437,21 +473,35 @@ #define CPU_AVR_ATMEGA128 0 #define CPU_AVR_ATMEGA1281 0 #define CPU_AVR_ATMEGA1280 0 + #define CPU_AVR_ATMEGA2560 0 #endif #if defined (__MSP430__) #define CPU_MSP430 1 #define CPU_ID msp430 - #define CPU_CORE_NAME "MSP430F2274" + #define CPU_CORE_NAME "MSP430" + + #if defined(__MSP430F2274__) + #define CPU_MSP430F2274 1 + #define CPU_NAME "MSP430F2274" + #else + #define CPU_MSP430F2274 0 + #endif - #if defined(__MSP430_2274__) - #define CPU_MSP430_2274 1 - #define CPU_NAME "2274" + #if defined(__MSP430G2231__) + #define CPU_MSP430G2231 1 + #define CPU_NAME "MSP430G2231" #else - #define CPU_MSP430_2274 0 + #define CPU_MSP430G2231 0 + #endif + + #if CPU_MSP430F2274 + CPU_MSP430G2231 != 1 + #error MSP430 CPU configuration error #endif #else - #define CPU_MSP430 0 + #define CPU_MSP430 0 + #define CPU_MSP430F2274 0 + #define CPU_MSP430G2231 0 #endif