X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fdetect.h;h=815e663d157f2cf1792a9b50e7b01b53b4504b45;hb=57fa5e371a8b40afc99b922731b77d17c55330a4;hp=3c4712d25f1fd72f8fbcfcd7657f75274a05d0b3;hpb=aa75cab12e97f7b9dea2219fecfe8c5188863297;p=bertos.git diff --git a/bertos/cpu/detect.h b/bertos/cpu/detect.h index 3c4712d2..815e663d 100644 --- a/bertos/cpu/detect.h +++ b/bertos/cpu/detect.h @@ -36,21 +36,17 @@ #ifndef CPU_DETECT_H #define CPU_DETECT_H -#if defined(__arm__) /* GCC */ \ - || defined(__ARM4TM__) /* IAR: defined for all cores >= 4tm */ - #define CPU_ARM 1 +#if defined(__ARM_ARCH_4T__) /* GCC */ \ + || (defined(__ICCARM__) && (__CORE__== __ARM4TM__)) /* IAR: defined for all cores == 4tm */ + #define CPU_ARM 1 + #define CPU_ID arm + #define CPU_CORE_NAME "ARM7TDMI" - // Cortex-M3 core family - #if defined(__ARM_LM3S1968__) - #define CPU_ID lm3s - #else - #define CPU_ID arm - #endif - - // AT91SAM7S core family + // AT91SAM7S products serie #if defined(__ARM_AT91SAM7S32__) #define CPU_ARM_AT91 1 #define CPU_ARM_AT91SAM7S32 1 + #define CPU_NAME "AT91SAM7S32" #else #define CPU_ARM_AT91SAM7S32 0 #endif @@ -59,6 +55,7 @@ #define CPU_ARM_AT91 1 #define CPU_ARM_SAM7S_LARGE 1 #define CPU_ARM_AT91SAM7S64 1 + #define CPU_NAME "AT91SAM7S64" #else #define CPU_ARM_AT91SAM7S64 0 #endif @@ -67,6 +64,7 @@ #define CPU_ARM_AT91 1 #define CPU_ARM_SAM7S_LARGE 1 #define CPU_ARM_AT91SAM7S128 1 + #define CPU_NAME "AT91SAM7S128" #else #define CPU_ARM_AT91SAM7S128 0 #endif @@ -75,6 +73,7 @@ #define CPU_ARM_AT91 1 #define CPU_ARM_SAM7S_LARGE 1 #define CPU_ARM_AT91SAM7S256 1 + #define CPU_NAME "AT91SAM7S256" #else #define CPU_ARM_AT91SAM7S256 0 #endif @@ -83,15 +82,17 @@ #define CPU_ARM_AT91 1 #define CPU_ARM_SAM7S_LARGE 1 #define CPU_ARM_AT91SAM7S512 1 + #define CPU_NAME "AT91SAM7S512" #else #define CPU_ARM_AT91SAM7S512 0 #endif - // AT91SAM7X core family + // AT91SAM7X products serie #if defined(__ARM_AT91SAM7X128__) #define CPU_ARM_AT91 1 #define CPU_ARM_SAM7X 1 #define CPU_ARM_AT91SAM7X128 1 + #define CPU_NAME "AT91SAM7X128" #else #define CPU_ARM_AT91SAM7X128 0 #endif @@ -100,6 +101,7 @@ #define CPU_ARM_AT91 1 #define CPU_ARM_SAM7X 1 #define CPU_ARM_AT91SAM7X256 1 + #define CPU_NAME "AT91SAM7X256" #else #define CPU_ARM_AT91SAM7X256 0 #endif @@ -109,23 +111,18 @@ #define CPU_ARM_AT91 1 #define CPU_ARM_SAM7X 1 #define CPU_ARM_AT91SAM7X512 1 + #define CPU_NAME "AT91SAM7X512" #else #define CPU_ARM_AT91SAM7X512 0 #endif - #if defined (__ARM_LM3S1968__) - #define CPU_ARM_LM3S 1 - #define CPU_ARM_LM3S1968 1 - #else - #define CPU_ARM_LM3S1968 0 - #endif - #if defined(__ARM_LPC2378__) #define CPU_ARM_LPC2 1 #define CPU_ARM_LPC2378 1 + #define CPU_NAME "LPC2378" #else #define CPU_ARM_LPC2378 0 - #endif + #endif #if !defined(CPU_ARM_SAM7S_LARGE) #define CPU_ARM_SAM7S_LARGE 0 @@ -144,32 +141,22 @@ + CPU_ARM_AT91SAM7X512 != 1 #error ARM CPU configuration error #endif - #define CPU_ARM_LM3S 0 #define CPU_ARM_LPC2 0 - #elif defined (CPU_ARM_LM3S) - #if CPU_ARM_LM3S1968 + 0 != 1 - #error Luminary ARM CPU configuration error - #endif - #define CPU_ARM_AT91 0 - #define CPU_ARM_LPC2 0 #elif defined (CPU_ARM_LPC2) - + #if CPU_ARM_LPC2378 + 0 != 1 #error NXP LPC2xxx ARM CPU configuration error #endif #define CPU_ARM_AT91 0 - #define CPU_ARM_LM3S 0 /* #elif Add other ARM families here */ #else #define CPU_ARM_AT91 0 - #define CPU_ARM_LM3S 0 #define CPU_ARM_LPC2 0 #endif - #if CPU_ARM_AT91 + CPU_ARM_LM3S \ - + CPU_ARM_LPC2 + 0 /* Add other ARM families here */ != 1 + #if CPU_ARM_AT91 + CPU_ARM_LPC2 + 0 /* Add other ARM families here */ != 1 #error ARM CPU configuration error #endif #else @@ -177,7 +164,6 @@ /* ARM Families */ #define CPU_ARM_AT91 0 - #define CPU_ARM_LM3S 0 #define CPU_ARM_LPC2 0 /* SAM7 sub-families */ @@ -194,13 +180,184 @@ #define CPU_ARM_AT91SAM7X256 0 #define CPU_ARM_AT91SAM7X512 0 - #define CPU_ARM_LM3S1968 0 - #define CPU_ARM_LPC2378 0 #endif +#if defined(__ARM_ARCH_7M__) /* GCC */ \ + || (defined(__ICCARM__) && (__CORE__== __ARM7M__)) /* IAR: defined for all cores v7M */ + /* Cortex-M3 */ + #define CPU_CM3 1 + #define CPU_ID cm3 + #define CPU_CORE_NAME "Cortex-M3" + + #if defined (__ARM_LM3S1968__) + #define CPU_CM3_LM3S 1 + #define CPU_CM3_LM3S1968 1 + #define CPU_NAME "LM3S1968" + #else + #define CPU_CM3_LM3S1968 0 + #endif + + #if defined (__ARM_LM3S8962__) + #define CPU_CM3_LM3S 1 + #define CPU_CM3_LM3S8962 1 + #define CPU_NAME "LM3S8962" + #else + #define CPU_CM3_LM3S8962 0 + #endif + + #if defined (__ARM_STM32F100RB__) + #define CPU_CM3_STM32 1 + #define CPU_CM3_STM32F100RB 1 + #define CPU_NAME "STM32F100RB" + #else + #define CPU_CM3_STM32F100RB 0 + #endif + + #if defined (__ARM_STM32F101C4__) + #define CPU_CM3_STM32 1 + #define CPU_CM3_STM32F101C4 1 + #define CPU_NAME "STM32F101C4" + #else + #define CPU_CM3_STM32F101C4 0 + #endif + + #if defined (__ARM_STM32F102C4__) + #define CPU_CM3_STM32 1 + #define CPU_CM3_STM32F102C4 1 + #define CPU_NAME "STM32F102C4" + #else + #define CPU_CM3_STM32F102C4 0 + #endif + + #if defined (__ARM_STM32F103RB__) + #define CPU_CM3_STM32 1 + #define CPU_CM3_STM32F103RB 1 + #define CPU_NAME "STM32F103RB" + #else + #define CPU_CM3_STM32F103RB 0 + #endif + + #if defined (__ARM_STM32F103RE__) + #define CPU_CM3_STM32 1 + #define CPU_CM3_STM32F103RE 1 + #define CPU_NAME "STM32F103RE" + #else + #define CPU_CM3_STM32F103RE 0 + #endif + + // AT91SAM3N products serie + #if defined (__ARM_SAM3N4__) + #define CPU_CM3_SAM3 1 + #define CPU_CM3_SAM3N 1 + #define CPU_CM3_SAM3N4 1 + #define CPU_NAME "SAM3N4" + + #define CPU_CM3_SAM3S 0 + #define CPU_CM3_SAM3U 0 + #define CPU_CM3_SAM3N2 0 + #define CPU_CM3_SAM3N1 0 + #define CPU_CM3_SAM3X 0 + #else + #define CPU_CM3_SAM3N4 0 + #endif + + // AT91SAM3S products serie + #if defined (__ARM_SAM3S4__) + #define CPU_CM3_SAM3 1 + #define CPU_CM3_SAM3S 1 + #define CPU_CM3_SAM3S4 1 + #define CPU_NAME "SAM3S4" + + #define CPU_CM3_SAM3N 0 + #define CPU_CM3_SAM3U 0 + #define CPU_CM3_SAM3X 0 + #else + #define CPU_CM3_SAM3S4 0 + #endif + + // AT91SAM3U products serie + #if defined (__ARM_SAM3U4__) + #define CPU_CM3_SAM3 1 + #define CPU_CM3_SAM3U 1 + #define CPU_CM3_SAM3U4 1 + #define CPU_NAME "SAM3U4" + + #define CPU_CM3_SAM3N 0 + #define CPU_CM3_SAM3S 0 + #define CPU_CM3_SAM3X 0 + #else + #define CPU_CM3_SAM3U4 0 + #endif + + // AT91SAM3X products serie + #if defined (__ARM_SAM3X8__) + #define CPU_CM3_SAM3 1 + #define CPU_CM3_SAM3X 1 + #define CPU_CM3_SAM3X8 1 + #define CPU_NAME "SAM3X8" + + #define CPU_CM3_SAM3N 0 + #define CPU_CM3_SAM3S 0 + #define CPU_CM3_SAM3U 0 + #else + #define CPU_CM3_SAM3X8 0 + #endif + + #if defined (CPU_CM3_LM3S) + #if CPU_CM3_LM3S1968 + CPU_CM3_LM3S8962 + 0 != 1 + #error Luminary Cortex-M3 CPU configuration error + #endif + #define CPU_CM3_STM32 0 + #define CPU_CM3_SAM3 0 + #elif defined (CPU_CM3_STM32) + #if CPU_CM3_STM32F100RB + CPU_CM3_STM32F101C4 + CPU_CM3_STM32F103RB + CPU_CM3_STM32F103RE + CPU_CM3_STM32F102C4 + 0 != 1 + #error STM32 Cortex-M3 CPU configuration error + #endif + #define CPU_CM3_LM3S 0 + #define CPU_CM3_SAM3 0 + #elif defined (CPU_CM3_SAM3) + #if CPU_CM3_SAM3N + CPU_CM3_SAM3U + CPU_CM3_SAM3S + CPU_CM3_SAM3X + 0 != 1 + #error SAM3 Cortex-M3 CPU configuration error + #endif + #if CPU_CM3_SAM3N4 + CPU_CM3_SAM3S4 + CPU_CM3_SAM3U4 + CPU_CM3_SAM3X8 + 0 != 1 + #error SAM3 Cortex-M3 CPU configuration error + #endif + #define CPU_CM3_LM3S 0 + #define CPU_CM3_STM32 0 + /* #elif Add other Cortex-M3 families here */ + #else + #define CPU_CM3_LM3S 0 + #define CPU_CM3_STM32 0 + #define CPU_CM3_SAM3 0 + #endif + + + #if CPU_CM3_LM3S + CPU_CM3_STM32 + CPU_CM3_SAM3 + 0 /* Add other Cortex-M3 families here */ != 1 + #error Cortex-M3 CPU configuration error + #endif + +#else + #define CPU_CM3 0 + #define CPU_CM3_LM3S 0 + #define CPU_CM3_LM3S1968 0 + #define CPU_CM3_LM3S8962 0 + + #define CPU_CM3_STM32 0 + #define CPU_CM3_STM32F100RB 0 + #define CPU_CM3_STM32F103RB 0 + #define CPU_CM3_STM32F101C4 0 + #define CPU_CM3_STM32F103RE 0 + + #define CPU_CM3_SAM3 0 + #define CPU_CM3_SAM3N 0 + #define CPU_CM3_SAM3N4 0 + #define CPU_CM3_SAM3X 0 + #define CPU_CM3_SAM3X8 0 +#endif + #if (defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC)) \ - && !defined(__ARM4TM__) /* IAR: if not ARM assume I196 */ + && !defined(__ICCARM__) /* IAR: if not ARM assume I196 */ #warning Assuming CPU is I196 #define CPU_I196 1 #define CPU_ID i196 @@ -214,12 +371,16 @@ #define CPU_X86_32 1 #define CPU_X86_64 0 #define CPU_ID x86 + #define CPU_CORE_NAME "x86" + #define CPU_NAME "generic" #elif defined(__x86_64__) /* GCC */ \ || (defined(_M_IX86) && defined(_WIN64)) /* MSVC */ #define CPU_X86 1 #define CPU_X86_32 0 #define CPU_X86_64 1 #define CPU_ID x86 + #define CPU_CORE_NAME "x86_64" + #define CPU_NAME "generic" #else #define CPU_X86 0 #define CPU_I386 0 @@ -255,61 +416,171 @@ #if defined (__AVR__) #define CPU_AVR 1 #define CPU_ID avr + #define CPU_CORE_NAME "AVR" #if defined(__AVR_ATmega32__) + #define CPU_AVR_MEGA 1 #define CPU_AVR_ATMEGA32 1 + #define CPU_NAME "ATmega32" #else #define CPU_AVR_ATMEGA32 0 #endif #if defined(__AVR_ATmega64__) + #define CPU_AVR_MEGA 1 #define CPU_AVR_ATMEGA64 1 + #define CPU_NAME "ATmega64" #else #define CPU_AVR_ATMEGA64 0 #endif #if defined(__AVR_ATmega103__) + #define CPU_AVR_MEGA 1 #define CPU_AVR_ATMEGA103 1 + #define CPU_NAME "ATmega103" #else #define CPU_AVR_ATMEGA103 0 #endif #if defined(__AVR_ATmega128__) + #define CPU_AVR_MEGA 1 #define CPU_AVR_ATMEGA128 1 + #define CPU_NAME "ATmega128" #else #define CPU_AVR_ATMEGA128 0 #endif #if defined(__AVR_ATmega8__) + #define CPU_AVR_MEGA 1 #define CPU_AVR_ATMEGA8 1 + #define CPU_NAME "ATmega8" #else #define CPU_AVR_ATMEGA8 0 #endif #if defined(__AVR_ATmega168__) + #define CPU_AVR_MEGA 1 #define CPU_AVR_ATMEGA168 1 + #define CPU_NAME "ATmega168" #else #define CPU_AVR_ATMEGA168 0 #endif #if defined(__AVR_ATmega328P__) + #define CPU_AVR_MEGA 1 #define CPU_AVR_ATMEGA328P 1 + #define CPU_NAME "ATmega328P" #else #define CPU_AVR_ATMEGA328P 0 #endif #if defined(__AVR_ATmega1281__) + #define CPU_AVR_MEGA 1 #define CPU_AVR_ATMEGA1281 1 + #define CPU_NAME "ATmega1281" #else #define CPU_AVR_ATMEGA1281 0 #endif + #if defined(__AVR_ATmega1280__) + #define CPU_AVR_MEGA 1 + #define CPU_AVR_ATMEGA1280 1 + #define CPU_NAME "ATmega1280" + #else + #define CPU_AVR_ATMEGA1280 0 + #endif + + #if defined(__AVR_ATmega2560__) + #define CPU_AVR_MEGA 1 + #define CPU_AVR_ATMEGA2560 1 + #define CPU_NAME "ATmega2560" + #else + #define CPU_AVR_ATMEGA2560 0 + #endif + + #if defined(__AVR_ATxmega128A1__) + #define CPU_AVR_XMEGA 1 + #define CPU_AVR_XMEGA_D4 0 + #define CPU_AVR_XMEGA_D3 0 + #define CPU_AVR_XMEGA_A4 0 + #define CPU_AVR_XMEGA_A3 0 + #define CPU_AVR_XMEGA_A1 1 + #define CPU_AVR_ATXMEGA128A1 1 + #define CPU_NAME "ATxmega128a1" + #else + #define CPU_AVR_ATXMEGA128A1 0 + #endif + + #if defined(__AVR_ATxmega64A3__) + #define CPU_AVR_XMEGA 1 + #define CPU_AVR_XMEGA_D4 0 + #define CPU_AVR_XMEGA_D3 0 + #define CPU_AVR_XMEGA_A4 0 + #define CPU_AVR_XMEGA_A3 1 + #define CPU_AVR_XMEGA_A1 0 + #define CPU_AVR_ATXMEGA64A3 1 + #define CPU_NAME "ATxmega64a3" + #else + #define CPU_AVR_ATXMEGA64A3 0 + #endif + + #if defined(__AVR_ATxmega32A4__) + #define CPU_AVR_XMEGA 1 + #define CPU_AVR_XMEGA_D4 0 + #define CPU_AVR_XMEGA_D3 0 + #define CPU_AVR_XMEGA_A4 1 + #define CPU_AVR_XMEGA_A3 0 + #define CPU_AVR_XMEGA_A1 0 + #define CPU_AVR_ATXMEGA32A4 1 + #define CPU_NAME "ATxmega32a4" + #else + #define CPU_AVR_ATXMEGA32A4 0 + #endif + + #if defined(__AVR_ATxmega32D4__) + #define CPU_AVR_XMEGA 1 + #define CPU_AVR_XMEGA_D4 1 + #define CPU_AVR_XMEGA_D3 0 + #define CPU_AVR_XMEGA_A4 0 + #define CPU_AVR_XMEGA_A3 0 + #define CPU_AVR_XMEGA_A1 0 + #define CPU_AVR_ATXMEGA32D4 1 + #define CPU_NAME "ATxmega32d4" + #else + #define CPU_AVR_ATXMEGA32D4 0 + #endif + #if CPU_AVR_ATMEGA32 + CPU_AVR_ATMEGA64 + CPU_AVR_ATMEGA103 + CPU_AVR_ATMEGA128 \ - + CPU_AVR_ATMEGA8 + CPU_AVR_ATMEGA168 + CPU_AVR_ATMEGA328P + CPU_AVR_ATMEGA1281 != 1 + + CPU_AVR_ATMEGA8 + CPU_AVR_ATMEGA168 + CPU_AVR_ATMEGA328P + CPU_AVR_ATMEGA1281 \ + + CPU_AVR_ATMEGA1280 + CPU_AVR_ATMEGA2560 + CPU_AVR_ATXMEGA128A1 + CPU_AVR_ATXMEGA64A3 \ + + CPU_AVR_ATXMEGA32A4 + CPU_AVR_ATXMEGA32D4 != 1 + #error AVR CPU configuration error + #endif + + #if defined(CPU_AVR_XMEGA) && defined(CPU_AVR_MEGA) + #error CPU cannot be MEGA and XMEGA + #elif defined(CPU_AVR_MEGA) + #define CPU_AVR_XMEGA 0 + #define CPU_AVR_XMEGA_D4 0 + #define CPU_AVR_XMEGA_D3 0 + #define CPU_AVR_XMEGA_A4 0 + #define CPU_AVR_XMEGA_A3 0 + #define CPU_AVR_XMEGA_A1 0 + #elif defined(CPU_AVR_XMEGA) + #define CPU_AVR_MEGA 0 + #if CPU_AVR_XMEGA_D4 + CPU_AVR_XMEGA_D3 + CPU_AVR_XMEGA_A4 \ + + CPU_AVR_XMEGA_A3 + CPU_AVR_XMEGA_A1 != 1 + #error AVR XMEGA CPU Configuration error + #endif + #endif + + #if CPU_AVR_MEGA + CPU_AVR_XMEGA != 1 #error AVR CPU configuration error #endif + #else #define CPU_AVR 0 + #define CPU_AVR_MEGA 0 #define CPU_AVR_ATMEGA8 0 #define CPU_AVR_ATMEGA168 0 #define CPU_AVR_ATMEGA328P 0 @@ -318,15 +589,55 @@ #define CPU_AVR_ATMEGA103 0 #define CPU_AVR_ATMEGA128 0 #define CPU_AVR_ATMEGA1281 0 + #define CPU_AVR_ATMEGA1280 0 + #define CPU_AVR_ATMEGA2560 0 + #define CPU_AVR_XMEGA 0 + #define CPU_AVR_XMEGA_D4 0 + #define CPU_AVR_XMEGA_D3 0 + #define CPU_AVR_XMEGA_A4 0 + #define CPU_AVR_XMEGA_A3 0 + #define CPU_AVR_XMEGA_A1 0 + #define CPU_AVR_ATXMEGA128A1 0 + #define CPU_AVR_ATXMEGA64A3 0 + #define CPU_AVR_XTMEGA32A4 0 + #define CPU_AVR_ATXMEGA32D4 0 +#endif + +#if defined (__MSP430__) + #define CPU_MSP430 1 + #define CPU_ID msp430 + #define CPU_CORE_NAME "MSP430" + + #if defined(__MSP430F2274__) + #define CPU_MSP430F2274 1 + #define CPU_NAME "MSP430F2274" + #else + #define CPU_MSP430F2274 0 + #endif + + #if defined(__MSP430G2231__) + #define CPU_MSP430G2231 1 + #define CPU_NAME "MSP430G2231" + #else + #define CPU_MSP430G2231 0 + #endif + + #if CPU_MSP430F2274 + CPU_MSP430G2231 != 1 + #error MSP430 CPU configuration error + #endif +#else + #define CPU_MSP430 0 + #define CPU_MSP430F2274 0 + #define CPU_MSP430G2231 0 #endif /* Self-check for the detection: only one CPU must be detected */ -#if CPU_ARM + CPU_I196 + CPU_X86 + CPU_PPC + CPU_DSP56K + CPU_AVR == 0 +#if CPU_ARM + CPU_CM3 + CPU_I196 + CPU_X86 + CPU_PPC + CPU_DSP56K + CPU_AVR + CPU_MSP430 == 0 #error Unknown CPU #elif !defined(CPU_ID) #error CPU_ID not defined -#elif CPU_ARM + CPU_I196 + CPU_X86 + CPU_PPC + CPU_DSP56K + CPU_AVR != 1 +#elif CPU_ARM + CPU_CM3 + CPU_I196 + CPU_X86 + CPU_PPC + CPU_DSP56K + CPU_AVR + CPU_MSP430 != 1 #error Internal CPU configuration error #endif