X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fdetect.h;h=8e1a69faf2764cec6d7aaf3dd40422939ee865d5;hb=e2cdc8384c68cea178b0e585bb4467dae454b449;hp=91ad6be2b441853e6cc9e8bb2c8a058ac3c90107;hpb=b81452356d9c25c75b420ba611979d60b4e3ecfa;p=bertos.git diff --git a/bertos/cpu/detect.h b/bertos/cpu/detect.h index 91ad6be2..8e1a69fa 100644 --- a/bertos/cpu/detect.h +++ b/bertos/cpu/detect.h @@ -36,10 +36,10 @@ #ifndef CPU_DETECT_H #define CPU_DETECT_H -#if defined(__arm__) /* GCC */ \ +#if defined(__ARM_ARCH_4T__) /* GCC */ \ || defined(__ARM4TM__) /* IAR: defined for all cores >= 4tm */ - #define CPU_ARM 1 - #define CPU_ID arm + #define CPU_ARM 1 + #define CPU_ID arm // AT91SAM7S core family #if defined(__ARM_AT91SAM7S32__) @@ -51,6 +51,7 @@ #if defined(__ARM_AT91SAM7S64__) #define CPU_ARM_AT91 1 + #define CPU_ARM_SAM7S_LARGE 1 #define CPU_ARM_AT91SAM7S64 1 #else #define CPU_ARM_AT91SAM7S64 0 @@ -58,6 +59,7 @@ #if defined(__ARM_AT91SAM7S128__) #define CPU_ARM_AT91 1 + #define CPU_ARM_SAM7S_LARGE 1 #define CPU_ARM_AT91SAM7S128 1 #else #define CPU_ARM_AT91SAM7S128 0 @@ -65,14 +67,24 @@ #if defined(__ARM_AT91SAM7S256__) #define CPU_ARM_AT91 1 + #define CPU_ARM_SAM7S_LARGE 1 #define CPU_ARM_AT91SAM7S256 1 #else #define CPU_ARM_AT91SAM7S256 0 #endif + #if defined(__ARM_AT91SAM7S512__) + #define CPU_ARM_AT91 1 + #define CPU_ARM_SAM7S_LARGE 1 + #define CPU_ARM_AT91SAM7S512 1 + #else + #define CPU_ARM_AT91SAM7S512 0 + #endif + // AT91SAM7X core family #if defined(__ARM_AT91SAM7X128__) #define CPU_ARM_AT91 1 + #define CPU_ARM_SAM7X 1 #define CPU_ARM_AT91SAM7X128 1 #else #define CPU_ARM_AT91SAM7X128 0 @@ -80,26 +92,61 @@ #if defined(__ARM_AT91SAM7X256__) #define CPU_ARM_AT91 1 + #define CPU_ARM_SAM7X 1 #define CPU_ARM_AT91SAM7X256 1 #else #define CPU_ARM_AT91SAM7X256 0 #endif + #if defined(__ARM_AT91SAM7X512__) + #define CPU_ARM_AT91 1 + #define CPU_ARM_SAM7X 1 + #define CPU_ARM_AT91SAM7X512 1 + #else + #define CPU_ARM_AT91SAM7X512 0 + #endif + + #if defined(__ARM_LPC2378__) + #define CPU_ARM_LPC2 1 + #define CPU_ARM_LPC2378 1 + #else + #define CPU_ARM_LPC2378 0 + #endif + + #if !defined(CPU_ARM_SAM7S_LARGE) + #define CPU_ARM_SAM7S_LARGE 0 + #endif + + #if !defined(CPU_ARM_SAM7X) + #define CPU_ARM_SAM7X 0 + #endif + + #if defined(CPU_ARM_AT91) #if CPU_ARM_AT91SAM7S32 + CPU_ARM_AT91SAM7S64 \ + CPU_ARM_AT91SAM7S128 + CPU_ARM_AT91SAM7S256 \ - + CPU_ARM_AT91SAM7X128 + CPU_ARM_AT91SAM7X256 != 1 + + CPU_ARM_AT91SAM7S512 \ + + CPU_ARM_AT91SAM7X128 + CPU_ARM_AT91SAM7X256 \ + + CPU_ARM_AT91SAM7X512 != 1 #error ARM CPU configuration error #endif + #define CPU_ARM_LPC2 0 + + #elif defined (CPU_ARM_LPC2) + #if CPU_ARM_LPC2378 + 0 != 1 + #error NXP LPC2xxx ARM CPU configuration error + #endif + #define CPU_ARM_AT91 0 /* #elif Add other ARM families here */ #else - #define CPU_ARM_AT91 0 + #define CPU_ARM_AT91 0 + #define CPU_ARM_LPC2 0 #endif - #if CPU_ARM_AT91 + 0 /* Add other ARM families here */ != 1 + #if CPU_ARM_AT91 + CPU_ARM_LPC2 + 0 /* Add other ARM families here */ != 1 #error ARM CPU configuration error #endif #else @@ -107,14 +154,84 @@ /* ARM Families */ #define CPU_ARM_AT91 0 + #define CPU_ARM_LPC2 0 + + /* SAM7 sub-families */ + #define CPU_ARM_SAM7S_LARGE 0 + #define CPU_ARM_SAM7X 0 /* ARM CPUs */ #define CPU_ARM_AT91SAM7S32 0 #define CPU_ARM_AT91SAM7S64 0 #define CPU_ARM_AT91SAM7S128 0 #define CPU_ARM_AT91SAM7S256 0 + #define CPU_ARM_AT91SAM7S512 0 #define CPU_ARM_AT91SAM7X128 0 #define CPU_ARM_AT91SAM7X256 0 + #define CPU_ARM_AT91SAM7X512 0 + + #define CPU_ARM_LPC2378 0 +#endif + +#if defined(__ARM_ARCH_7M__) + /* Cortex-M3 */ + #define CPU_CM3 1 + #define CPU_ID cm3 + + #if defined (__ARM_LM3S1968__) + #define CPU_CM3_LM3S 1 + #define CPU_CM3_LM3S1968 1 + #else + #define CPU_CM3_LM3S1968 0 + #endif + + #if defined (__ARM_LM3S8962__) + #define CPU_CM3_LM3S 1 + #define CPU_CM3_LM3S8962 1 + #else + #define CPU_CM3_LM3S8962 0 + #endif + + #if defined (__ARM_STM32F103R8__) + #define CPU_CM3_STM32 1 + #define CPU_CM3_STM32F103R8 1 + #else + #define CPU_CM3_STM32F103R8 0 + #endif + + #if defined (CPU_CM3_LM3S) + #if CPU_CM3_LM3S1968 + CPU_CM3_LM3S8962 + 0 != 1 + #error Luminary Cortex-M3 CPU configuration error + #endif + #define CPU_CM3_STM32 0 + #elif defined (CPU_CM3_STM32) + #if CPU_CM3_STM32F103R8 + 0 != 1 + #error STM32 Cortex-M3 CPU configuration error + #endif + #define CPU_CM3_LM3S 0 + /* #elif Add other Cortex-M3 families here */ + #else + #define CPU_CM3_LM3S 0 + #define CPU_CM3_STM32 0 + #endif + + + #if CPU_CM3_LM3S + CPU_CM3_STM32 + 0 /* Add other Cortex-M3 families here */ != 1 + #error Cortex-M3 CPU configuration error + #endif + +#else + #define CPU_CM3 0 + + #define CPU_CM3_LM3S 0 + + #define CPU_CM3_LM3S1968 0 + + #define CPU_CM3_LM3S8968 0 + + #define CPU_CM3_STM32 0 + + #define CPU_CM3_STM32F103R8 0 #endif #if (defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC)) \ @@ -174,6 +291,12 @@ #define CPU_AVR 1 #define CPU_ID avr + #if defined(__AVR_ATmega32__) + #define CPU_AVR_ATMEGA32 1 + #else + #define CPU_AVR_ATMEGA32 0 + #endif + #if defined(__AVR_ATmega64__) #define CPU_AVR_ATMEGA64 1 #else @@ -204,20 +327,28 @@ #define CPU_AVR_ATMEGA168 0 #endif + #if defined(__AVR_ATmega328P__) + #define CPU_AVR_ATMEGA328P 1 + #else + #define CPU_AVR_ATMEGA328P 0 + #endif + #if defined(__AVR_ATmega1281__) #define CPU_AVR_ATMEGA1281 1 #else #define CPU_AVR_ATMEGA1281 0 #endif - #if CPU_AVR_ATMEGA64 + CPU_AVR_ATMEGA103 + CPU_AVR_ATMEGA128 \ - + CPU_AVR_ATMEGA8 + CPU_AVR_ATMEGA168 + CPU_AVR_ATMEGA1281 != 1 + #if CPU_AVR_ATMEGA32 + CPU_AVR_ATMEGA64 + CPU_AVR_ATMEGA103 + CPU_AVR_ATMEGA128 \ + + CPU_AVR_ATMEGA8 + CPU_AVR_ATMEGA168 + CPU_AVR_ATMEGA328P + CPU_AVR_ATMEGA1281 != 1 #error AVR CPU configuration error #endif #else #define CPU_AVR 0 #define CPU_AVR_ATMEGA8 0 #define CPU_AVR_ATMEGA168 0 + #define CPU_AVR_ATMEGA328P 0 + #define CPU_AVR_ATMEGA32 0 #define CPU_AVR_ATMEGA64 0 #define CPU_AVR_ATMEGA103 0 #define CPU_AVR_ATMEGA128 0 @@ -226,11 +357,11 @@ /* Self-check for the detection: only one CPU must be detected */ -#if CPU_ARM + CPU_I196 + CPU_X86 + CPU_PPC + CPU_DSP56K + CPU_AVR == 0 +#if CPU_ARM + CPU_CM3 + CPU_I196 + CPU_X86 + CPU_PPC + CPU_DSP56K + CPU_AVR == 0 #error Unknown CPU #elif !defined(CPU_ID) #error CPU_ID not defined -#elif CPU_ARM + CPU_I196 + CPU_X86 + CPU_PPC + CPU_DSP56K + CPU_AVR != 1 +#elif CPU_ARM + CPU_CM3 + CPU_I196 + CPU_X86 + CPU_PPC + CPU_DSP56K + CPU_AVR != 1 #error Internal CPU configuration error #endif