X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fframe.h;h=63d341cf1db379d159d3f4b0d99e162ece2a9e5f;hb=485f68165577f92d04057771bd11e969be9a2c7c;hp=8cb7a813d5a2192c9afe1c47dda4616042008ed4;hpb=323384a01ed8500f48081f88754d1495d63eff4c;p=bertos.git

diff --git a/bertos/cpu/frame.h b/bertos/cpu/frame.h
index 8cb7a813..63d341cf 100644
--- a/bertos/cpu/frame.h
+++ b/bertos/cpu/frame.h
@@ -51,51 +51,27 @@
 #include <cfg/compiler.h>      /* for uintXX_t */
 
 #if CPU_X86
-
-	#define CPU_SAVED_REGS_CNT      7
+	#if CPU_X86_32
+		#define CPU_SAVED_REGS_CNT      2
+	#elif CPU_X86_64
+		#define CPU_SAVED_REGS_CNT      8
+	#else
+		#error "unknown CPU"
+	#endif
 	#define CPU_STACK_GROWS_UPWARD  0
 	#define CPU_SP_ON_EMPTY_SLOT	0
 
 #elif CPU_ARM
 
-	#define CPU_SAVED_REGS_CNT     10
+	#define CPU_SAVED_REGS_CNT     8
 	#define CPU_STACK_GROWS_UPWARD 0
 	#define CPU_SP_ON_EMPTY_SLOT   0
 
+#elif CPU_CM3
 
-	EXTERN_C void asm_proc_entry(void);
-	/**
-	 * Initialization value for registers in stack frame.
-	 * For the CPSR register, the initial value is set to:
-	 * - All flags (N, Z, C, V) set to 0.
-	 * - IRQ and FIQ enabled.
-	 * - ARM state.
-	 * - CPU in Supervisor Mode (SVC).
-	 */
-	#define CPU_CREATE_NEW_STACK(stack, entry, exit) \
-	do { \
-		/* LR (asm proc_entry trampoline) */ \
-		CPU_PUSH_CALL_FRAME(stack, asm_proc_entry); \
-		/* R11 (Process entry point) DO NOT CHANGE: asm_proc_entry expects \
-		 * to find the actual process entry point in R11 */ \
-		CPU_PUSH_CALL_FRAME(stack, entry); \
-		/* R10 */ \
-		CPU_PUSH_WORD(stack, 0x10101010); \
-		/* R9 */ \
-		CPU_PUSH_WORD(stack, 0x09090909); \
-		/* R8 */ \
-		CPU_PUSH_WORD(stack, 0x08080808); \
-		/* R7 */ \
-		CPU_PUSH_WORD(stack, 0x07070707); \
-		/* R6 */ \
-		CPU_PUSH_WORD(stack, 0x06060606); \
-		/* R5 */ \
-		CPU_PUSH_WORD(stack, 0x05050505); \
-		/* R4 */ \
-		CPU_PUSH_WORD(stack, 0x04040404); \
-		/* CPSR */ \
-		CPU_PUSH_WORD(stack, 0x00000013); \
-	} while (0)
+	#define CPU_SAVED_REGS_CNT     8
+	#define CPU_STACK_GROWS_UPWARD 0
+	#define CPU_SP_ON_EMPTY_SLOT   0
 
 #elif CPU_PPC
 
@@ -111,17 +87,15 @@
 
 #elif CPU_AVR
 
-	#define CPU_SAVED_REGS_CNT     19
+	#define CPU_SAVED_REGS_CNT     18
 	#define CPU_STACK_GROWS_UPWARD  0
 	#define CPU_SP_ON_EMPTY_SLOT    1
 
-	/**
-	 * Initialization value for registers in stack frame.
-	 * The register index is not directly corrispondent to CPU
-	 * register numbers. Index 0 is the SREG register: the initial
-	 * value is all 0 but the interrupt bit (bit 7).
-	 */
-	#define CPU_REG_INIT_VALUE(reg) (reg == 0 ? 0x80 : 0)
+#elif CPU_MSP430
+
+	#define CPU_SAVED_REGS_CNT     16
+	#define CPU_STACK_GROWS_UPWARD  1
+	#define CPU_SP_ON_EMPTY_SLOT    0
 
 #else
 	#error No CPU_... defined.
@@ -137,7 +111,7 @@
 
 /// Default for macro not defined in the right arch section
 #ifndef CPU_REG_INIT_VALUE
-	#define CPU_REG_INIT_VALUE(reg)     0
+	#define CPU_REG_INIT_VALUE(reg)     (reg)
 #endif
 
 /*
@@ -187,6 +161,40 @@
 			CPU_PUSH_WORD((sp), 0x100); \
 		} while (0);
 
+#elif CPU_CM3
+
+	#if CONFIG_KERN_PREEMPT
+		INLINE void cm3_preempt_switch_context(cpu_stack_t **new_sp, cpu_stack_t **old_sp)
+		{
+			register cpu_stack_t **__new_sp asm ("r0") = new_sp;
+			register cpu_stack_t **__old_sp asm ("r1") = old_sp;
+
+			asm volatile ("svc #0"
+				: : "r"(__new_sp), "r"(__old_sp) : "memory", "cc");
+		}
+		#define asm_switch_context cm3_preempt_switch_context
+
+		#define CPU_CREATE_NEW_STACK(stack) \
+			do { \
+				size_t i; \
+				/* Initialize process stack frame */ \
+				CPU_PUSH_WORD((stack), 0x01000000);		/* xPSR    */	\
+				CPU_PUSH_WORD((stack), (cpu_stack_t)proc_entry);	/* pc      */	\
+				CPU_PUSH_WORD((stack), 0);				/* lr      */	\
+				CPU_PUSH_WORD((stack), 0);				/* ip	   */	\
+				CPU_PUSH_WORD((stack), 0);				/* r3      */	\
+				CPU_PUSH_WORD((stack), 0);				/* r2      */	\
+				CPU_PUSH_WORD((stack), 0);				/* r1      */	\
+				CPU_PUSH_WORD((stack), 0);				/* r0      */	\
+				CPU_PUSH_WORD((stack), 0xfffffffd);		/* lr_exc  */	\
+				/* Push a clean set of CPU registers for asm_switch_context() */ \
+				for (i = 0; i < CPU_SAVED_REGS_CNT; i++) \
+					CPU_PUSH_WORD(stack, CPU_REG_INIT_VALUE(i)); \
+				CPU_PUSH_WORD(stack, IRQ_PRIO_DISABLED); \
+			} while (0)
+
+	#endif /* CONFIG_KERN_PREEMPT */
+
 #elif CPU_AVR
 	/*
 	 * On AVR, addresses are pushed into the stack as little-endian, while
@@ -232,7 +240,9 @@
 			CPU_PUSH_WORD((sp), 0);                  /* CR -> 4(SP) */ \
 		} while (0)
 
-#else
+#endif
+
+#ifndef CPU_PUSH_CALL_FRAME
 	#define CPU_PUSH_CALL_FRAME(sp, func) \
 		CPU_PUSH_WORD((sp), (cpu_stack_t)(func))
 #endif
@@ -247,15 +257,7 @@
  * in hosted environments such as emulators.
  */
 #ifndef CPU_IDLE
-	#if defined(ARCH_QT) && (ARCH & ARCH_QT)
-		/* This emulator hook should yield the CPU to the host.  */
-		EXTERN_C_BEGIN
-		void emul_idle(void);
-		EXTERN_C_END
-		#define CPU_IDLE emul_idle()
-	#else /* !ARCH_EMUL */
-		#define CPU_IDLE do { /* nothing */ } while (0)
-	#endif /* !ARCH_EMUL */
+	#define CPU_IDLE PAUSE
 #endif /* !CPU_IDLE */
 
 /**
@@ -263,12 +265,11 @@
  */
 #ifndef CPU_CREATE_NEW_STACK
 
-	#define CPU_CREATE_NEW_STACK(stack, entry, exit) \
+	#define CPU_CREATE_NEW_STACK(stack) \
 		do { \
 			size_t i; \
 			/* Initialize process stack frame */ \
-			CPU_PUSH_CALL_FRAME(stack, exit); \
-			CPU_PUSH_CALL_FRAME(stack, entry); \
+			CPU_PUSH_CALL_FRAME(stack, proc_entry); \
 			/* Push a clean set of CPU registers for asm_switch_context() */ \
 			for (i = 0; i < CPU_SAVED_REGS_CNT; i++) \
 				CPU_PUSH_WORD(stack, CPU_REG_INIT_VALUE(i)); \