X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fframe.h;h=e8d0f898973458fe214c4ad1e5272b86ccda1ad1;hb=ad984bef9a7d5ca01b97eb8b14a655e64ea79cc9;hp=2244b3b1bf85a243ca1d1f407a365fd1bc99cf24;hpb=f709a37e5659fd591b5a61d80b45257105ac1850;p=bertos.git diff --git a/bertos/cpu/frame.h b/bertos/cpu/frame.h index 2244b3b1..e8d0f898 100644 --- a/bertos/cpu/frame.h +++ b/bertos/cpu/frame.h @@ -51,50 +51,27 @@ #include /* for uintXX_t */ #if CPU_X86 - - #define CPU_SAVED_REGS_CNT 7 + #if CPU_X86_32 + #define CPU_SAVED_REGS_CNT 2 + #elif CPU_X86_64 + #define CPU_SAVED_REGS_CNT 8 + #else + #error "unknown CPU" + #endif #define CPU_STACK_GROWS_UPWARD 0 #define CPU_SP_ON_EMPTY_SLOT 0 #elif CPU_ARM - #define CPU_SAVED_REGS_CNT 10 + #define CPU_SAVED_REGS_CNT 8 #define CPU_STACK_GROWS_UPWARD 0 #define CPU_SP_ON_EMPTY_SLOT 0 - /** - * Initialization value for registers in stack frame. - * For the CPSR register, the initial value is set to: - * - All flags (N, Z, C, V) set to 0. - * - IRQ and FIQ enabled. - * - ARM state. - * - CPU in Supervisor Mode (SVC). - */ - #define CPU_CREATE_NEW_STACK(stack, entry, exit) \ - do { \ - /* Process entry point */ \ - CPU_PUSH_CALL_FRAME(stack, entry); \ - /* LR (proc_exit) */ \ - CPU_PUSH_CALL_FRAME(stack, exit); \ - /* R11 */ \ - CPU_PUSH_WORD(stack, 0x11111111); \ - /* R10 */ \ - CPU_PUSH_WORD(stack, 0x10101010); \ - /* R9 */ \ - CPU_PUSH_WORD(stack, 0x09090909); \ - /* R8 */ \ - CPU_PUSH_WORD(stack, 0x08080808); \ - /* R7 */ \ - CPU_PUSH_WORD(stack, 0x07070707); \ - /* R6 */ \ - CPU_PUSH_WORD(stack, 0x06060606); \ - /* R5 */ \ - CPU_PUSH_WORD(stack, 0x05050505); \ - /* R4 */ \ - CPU_PUSH_WORD(stack, 0x04040404); \ - /* CPSR */ \ - CPU_PUSH_WORD(stack, 0x00000013); \ - } while (0) +#elif CPU_CM3 + + #define CPU_SAVED_REGS_CNT 8 + #define CPU_STACK_GROWS_UPWARD 0 + #define CPU_SP_ON_EMPTY_SLOT 0 #elif CPU_PPC @@ -110,18 +87,10 @@ #elif CPU_AVR - #define CPU_SAVED_REGS_CNT 19 + #define CPU_SAVED_REGS_CNT 18 #define CPU_STACK_GROWS_UPWARD 0 #define CPU_SP_ON_EMPTY_SLOT 1 - /** - * Initialization value for registers in stack frame. - * The register index is not directly corrispondent to CPU - * register numbers. Index 0 is the SREG register: the initial - * value is all 0 but the interrupt bit (bit 7). - */ - #define CPU_REG_INIT_VALUE(reg) (reg == 0 ? 0x80 : 0) - #else #error No CPU_... defined. #endif @@ -136,7 +105,7 @@ /// Default for macro not defined in the right arch section #ifndef CPU_REG_INIT_VALUE - #define CPU_REG_INIT_VALUE(reg) 0 + #define CPU_REG_INIT_VALUE(reg) (reg) #endif /* @@ -186,6 +155,15 @@ CPU_PUSH_WORD((sp), 0x100); \ } while (0); +#elif CPU_CM3 + + + #define CPU_PUSH_CALL_FRAME(sp, func) \ + do { \ + CPU_PUSH_WORD((sp), 0x01000000); /* xPSR */ \ + CPU_PUSH_WORD((sp), (cpu_stack_t)(func)); /* lr */ \ + } while (0); + #elif CPU_AVR /* * On AVR, addresses are pushed into the stack as little-endian, while @@ -246,28 +224,19 @@ * in hosted environments such as emulators. */ #ifndef CPU_IDLE - #if defined(ARCH_QT) && (ARCH & ARCH_QT) - /* This emulator hook should yield the CPU to the host. */ - EXTERN_C_BEGIN - void emul_idle(void); - EXTERN_C_END - #define CPU_IDLE emul_idle() - #else /* !ARCH_EMUL */ - #define CPU_IDLE do { /* nothing */ } while (0) - #endif /* !ARCH_EMUL */ + #define CPU_IDLE PAUSE #endif /* !CPU_IDLE */ /** * Default macro for creating a new Process stack - */ + */ #ifndef CPU_CREATE_NEW_STACK - #define CPU_CREATE_NEW_STACK(stack, entry, exit) \ + #define CPU_CREATE_NEW_STACK(stack) \ do { \ size_t i; \ /* Initialize process stack frame */ \ - CPU_PUSH_CALL_FRAME(stack, exit); \ - CPU_PUSH_CALL_FRAME(stack, entry); \ + CPU_PUSH_CALL_FRAME(stack, proc_entry); \ /* Push a clean set of CPU registers for asm_switch_context() */ \ for (i = 0; i < CPU_SAVED_REGS_CNT; i++) \ CPU_PUSH_WORD(stack, CPU_REG_INIT_VALUE(i)); \