X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fhw%2Fhw_sipo.h;h=a5d680ac1688905ac8bf630f7eb6f6d5e5f8d21c;hb=3c52f2762ac5af229124b6deb3a838c5afa47138;hp=ad02c57e0ed75cd139b17d9c112fce17405fd4bc;hpb=e423e63cade618baf616a79b99aaab5de74ec76e;p=bertos.git

diff --git a/bertos/hw/hw_sipo.h b/bertos/hw/hw_sipo.h
index ad02c57e..a5d680ac 100644
--- a/bertos/hw/hw_sipo.h
+++ b/bertos/hw/hw_sipo.h
@@ -46,6 +46,18 @@
 #warning TODO:This is an example implementation, you must implement it!
 
 
+/**
+ * Mapping sipo connection on board.
+ * See scheme to more info.
+ */
+typedef enum SipoMap {
+
+	/* Add device here */
+
+	SIPO_CNT
+} SipoMap;
+
+
 /**
  * Define the macros needed to set the serial input bit of SIPO device
  * low or high.
@@ -57,18 +69,47 @@
  * Drive pin to load the bit, presented in serial-in pin,
  * into sipo shift register.
  */
-#define SIPO_SI_CLOCK() /* Implement me! */
+#define SIPO_SI_CLOCK(clk_pol)
+	do { \
+		/* Implement me! */ \
+		(void)clk_pol; \
+	} while (0)
 
 /**
  * Clock the content of shift register to output.
  */
-#define SIPO_LOAD()   /* Implement me! */
+#define SIPO_LOAD(device, load_pol)  \
+	do { \
+		/* Implement me! */ \
+		(void)device; \
+		(void)load_pol; \
+	} while (0)
 
 /**
  * Enable the shift register output.
  */
 #define SIPO_ENABLE() /* Implement me! */
 
+/**
+ * Set logic level for load signal
+ */
+#define SIPO_SET_LD_LEVEL(device, load_pol) \
+	do { \
+		/* Implement me! */ \
+		(void)device; \
+		(void)load_pol; \
+	} while (0)
+
+
+/**
+ * Sel logic level for clock signal
+ */
+#define SIPO_SET_CLK_LEVEL(clock_pol)  \
+	do { \
+		/* Implement me! */ \
+		(void)clock_pol; \
+	} while (0)
+
 
 /**
  * Do everything needed in order to init the SIPO pins.