X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=boards%2Fek-lm3s1968%2Fhw%2Fhw_adc.h;h=1f6aeadd6f200eaab6aa0b58214cba231df5e1e7;hb=e5f2bd2aff866d5a3b3c2f22e1a14c244ee44229;hp=902a8b470bd51f2f5e4bbd7bee3b4270b83822d5;hpb=fc1f641a3e2b8cbb4597b605367b11ede313a09d;p=bertos.git

diff --git a/boards/ek-lm3s1968/hw/hw_adc.h b/boards/ek-lm3s1968/hw/hw_adc.h
index 902a8b47..1f6aeadd 100644
--- a/boards/ek-lm3s1968/hw/hw_adc.h
+++ b/boards/ek-lm3s1968/hw/hw_adc.h
@@ -39,7 +39,7 @@
 #define HW_ADC_H
 
 #include <drv/adc.h>
-#include <drv/timer.h>
+#include <drv/clock_lm3s.h>
 
 #include <io/cm3.h>
 
@@ -49,27 +49,47 @@
 INLINE uint16_t hw_readRawTemp(void)
 {
 	/* Trig the temperature sampling */
-	HWREG(ADC0_BASE + ADC_O_PSSI) = BV(3);
+	HWREG(ADC0_BASE + ADC_O_PSSI) |= ADC_PSSI_SS3;
+
+	/* Poll untill acquisition end */
+	while (!(HWREG(ADC0_BASE + ADC_O_SSFSTAT3) & ADC_SSFSTAT3_FULL));
 
 	return (uint16_t)HWREG(ADC0_BASE + ADC_O_SSFIFO3);
 }
 
-INLINE void hw_initIntTemp(void)
+/*
+ * Return the cpu core temperature in degrees C*100
+ */
+INLINE uint16_t hw_readIntTemp(void)
 {
+	/* Trig the temperature sampling */
+	HWREG(ADC0_BASE + ADC_O_PSSI) |= ADC_PSSI_SS3;
 
+	/* Poll untill acquisition end */
+	while (!(HWREG(ADC0_BASE + ADC_O_SSFSTAT3) & ADC_SSFSTAT3_FULL));
+
+	return (uint16_t)(14750 - ADC_RANGECONV(HWREG(ADC0_BASE + ADC_O_SSFIFO3), 0, 300) * 75);
+}
+
+INLINE void hw_initIntTemp(void)
+{
+	/* Enable ADC0 clock */
 	SYSCTL_RCGC0_R |= SYSCTL_RCGC0_ADC0;
 
-	/* Why this??? */
-	timer_udelay(1);
+	/*
+	 * We wait some time because the clock is istable
+	 * and that could cause system hardfault
+	 */
+	lm3s_busyWait(10);
 
 	/* Disable all sequence */
 	HWREG(ADC0_BASE + ADC_O_ACTSS) = 0;
 	/* Set trigger event to programmed (for all sequence) */
 	HWREG(ADC0_BASE + ADC_O_EMUX) = 0;
 	/* Enalbe read of temperature sensor */
-	HWREG(ADC0_BASE + ADC_O_SSCTL3) = BV(3);
+	HWREG(ADC0_BASE + ADC_O_SSCTL3) |= ADC_SSCTL3_TS0;
 	/* Enable sequence S03 (single sample on select channel) */
-	HWREG(ADC0_BASE + ADC_O_ACTSS) = BV(3);
+	HWREG(ADC0_BASE + ADC_O_ACTSS) |= ADC_ACTSS_ASEN3;
 }
 
 #endif /* HW_ADC_H */