X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=cfg%2Fcpu.h;h=23d0ddf1fe157b8893732dd0cd42471f699483b2;hb=c2fdd9fdabea8688dfe7d841c53b842a1ebe8a35;hp=c69b9c6f02129472c96de7de277361b21e09ba49;hpb=377c8e6cb7776c1b7d0368928fc619e20077b87f;p=bertos.git

diff --git a/cfg/cpu.h b/cfg/cpu.h
index c69b9c6f..23d0ddf1 100755
--- a/cfg/cpu.h
+++ b/cfg/cpu.h
@@ -1,4 +1,4 @@
-/*!
+/**
  * \file
  * <!--
  * Copyright 2004, 2005 Develer S.r.l. (http://www.develer.com/)
@@ -8,66 +8,29 @@
  *
  * \brief CPU-specific definitions
  *
- * \version $Id$
- *
  * \author Giovanni Bajo <rasky@develer.com>
  * \author Bernardo Innocenti <bernie@develer.com>
  * \author Stefano Fedrigo <aleph@develer.com>
  */
-
-/*#*
- *#* $Log$
- *#* Revision 1.5  2005/06/27 21:24:17  bernie
- *#* CPU_CSOURCE(): New macro.
- *#*
- *#* Revision 1.4  2005/06/14 06:15:10  bernie
- *#* Add X86_64 support.
- *#*
- *#* Revision 1.3  2005/04/12 04:06:17  bernie
- *#* Catch missing CPU earlier.
- *#*
- *#* Revision 1.2  2005/04/11 19:10:27  bernie
- *#* Include top-level headers from cfg/ subdir.
- *#*
- *#* Revision 1.1  2005/04/11 19:04:13  bernie
- *#* Move top-level headers to cfg/ subdir.
- *#*
- *#* Revision 1.30  2005/03/15 00:20:09  bernie
- *#* BREAKPOINT, IRQ_RUNNING(), IRQ_GETSTATE(): New DSP56K macros.
- *#*
- *#* Revision 1.29  2005/02/16 20:33:24  bernie
- *#* Preliminary PPC support.
- *#*
- *#* Revision 1.28  2004/12/31 17:39:41  bernie
- *#* Fix documentation.
- *#*
- *#* Revision 1.27  2004/12/31 17:02:47  bernie
- *#* IRQ_SAVE_DISABLE(), IRQ_RESTORE(): Add null stubs for x86.
- *#*
- *#* Revision 1.26  2004/12/13 12:08:12  bernie
- *#* DISABLE_IRQSAVE, ENABLE_IRQRESTORE, DISABLE_INTS, ENABLE_INTS: Remove obsolete macros.
- *#*
- *#* Revision 1.25  2004/12/08 08:31:02  bernie
- *#* CPU_HARVARD: Define to 1 for AVR and DSP56K.
- *#*/
 #ifndef DEVLIB_CPU_H
 #define DEVLIB_CPU_H
 
 #include <cfg/compiler.h> /* for uintXX_t */
+#include <cfg/arch_config.h>  /* ARCH_EMUL */
 
 
-/*!
+/**
  * \name Macros for determining CPU endianness.
  * \{
  */
 #define CPU_BIG_ENDIAN    0x1234
-#define CPU_LITTLE_ENDIAN 0x3412
+#define CPU_LITTLE_ENDIAN 0x3412 /* Look twice, pal. This is not a bug. */
 /*\}*/
 
-/*! Macro to include cpu-specific versions of the headers. */
+/** Macro to include cpu-specific versions of the headers. */
 #define CPU_HEADER(module)          PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).h)
 
-/*! Macro to include cpu-specific versions of implementation files. */
+/** Macro to include cpu-specific versions of implementation files. */
 #define CPU_CSOURCE(module)         PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).c)
 
 
@@ -90,14 +53,20 @@
 #elif CPU_X86
 
 	#define NOP                     asm volatile ("nop")
-	#define IRQ_DISABLE             FIXME
-	#define IRQ_ENABLE              FIXME
-	#define IRQ_SAVE_DISABLE(x)     FIXME
-	#define IRQ_RESTORE(x)          FIXME
 
-	typedef uint32_t cpuflags_t; // FIXME
+	/* Get IRQ_* definitions from the hosting environment. */
+	#include <cfg/os.h>
+	#if OS_EMBEDDED
+		#define IRQ_DISABLE             FIXME
+		#define IRQ_ENABLE              FIXME
+		#define IRQ_SAVE_DISABLE(x)     FIXME
+		#define IRQ_RESTORE(x)          FIXME
+		typedef uint32_t cpuflags_t; // FIXME
+	#endif /* OS_EMBEDDED */
+
 
 	#define CPU_REGS_CNT            7
+	#define CPU_SAVED_REGS_CNT      7
 	#define CPU_STACK_GROWS_UPWARD  0
 	#define CPU_SP_ON_EMPTY_SLOT	0
 	#define CPU_BYTE_ORDER          CPU_LITTLE_ENDIAN
@@ -116,8 +85,121 @@
 		#define CPU_REG_BITS    32
 	#endif
 
+#elif CPU_ARM
+
+	typedef uint32_t cpuflags_t;
+	typedef uint32_t cpustack_t;
+
+	/* Register counts include SREG too */
+	#define CPU_REG_BITS           32
+	#define CPU_REGS_CNT           16
+	#define CPU_SAVED_REGS_CNT     FIXME
+	#define CPU_STACK_GROWS_UPWARD 0  //FIXME
+	#define CPU_SP_ON_EMPTY_SLOT   0  //FIXME
+	#define CPU_BYTE_ORDER         (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
+	#define CPU_HARVARD            0
+
+	#ifdef __IAR_SYSTEMS_ICC__
+
+		#include <inarm.h>
+
+		#if __CPU_MODE__ == 1 /* Thumb */
+			/* Use stubs */
+			extern cpuflags_t get_CPSR(void);
+			extern void set_CPSR(cpuflags_t flags);
+		#else
+			#define get_CPSR __get_CPSR
+			#define set_CPSR __set_CPSR
+		#endif
+
+		#define NOP         __no_operation()
+		#define IRQ_DISABLE __disable_interrupt()
+		#define IRQ_ENABLE  __enable_interrupt()
+
+		#define IRQ_SAVE_DISABLE(x) \
+		do { \
+			(x) = get_CPSR(); \
+			__disable_interrupt(); \
+		} while (0)
+
+		#define IRQ_RESTORE(x) \
+		do { \
+			set_CPSR(x); \
+		} while (0)
+
+		#define IRQ_GETSTATE() \
+			((bool)(get_CPSR() & 0xb0))
+
+		#define BREAKPOINT  /* asm("bkpt 0") DOES NOT WORK */
+
+	#else /* !__IAR_SYSTEMS_ICC__ */
+
+		#warning "IRQ_ macros need testing!"
+
+		#define NOP         asm volatile ("mov r0,r0" ::)
+
+		#define IRQ_DISABLE \
+		do { \
+			asm volatile ( \
+				"mrs r0, cpsr\n\t" \
+				"orr r0, r0, #0xb0\n\t" \
+				"msr cpsr, r0" \
+				:: \
+			); \
+		} while (0)
+
+		#define IRQ_ENABLE \
+		do { \
+			asm volatile ( \
+				"mrs r0, cpsr\n\t" \
+				"bic r0, r0, #0xb0\n\t" \
+				"msr cpsr, r0" \
+				:: \
+			); \
+		} while (0)
+
+		#define IRQ_SAVE_DISABLE(x) \
+		do { \
+			asm volatile ( \
+				"mrs r0, cpsr\n\t" \
+				"mov %0, r0\n\t" \
+				"orr r0, r0, #0xb0\n\t" \
+				"msr cpsr, r0" \
+				: "=r" (x) \
+				: /* no inputs */ \
+				: "r0" \
+			); \
+		} while (0)
+
+		#define IRQ_RESTORE(x) \
+		do { \
+			asm volatile ( \
+				"mov r0, %0\n\t" \
+				"msr cpsr, r0" \
+				: /* no outputs */ \
+				: "r" (x) \
+				: "r0" \
+			); \
+		} while (0)
+
+		#define IRQ_GETSTATE() \
+		({ \
+			uint32_t sreg; \
+			asm volatile ( \
+				"mrs r0, cpsr\n\t" \
+				"mov %0, r0" \
+				: "=r" (sreg) \
+				: /* no inputs */ \
+				: "r0" \
+			); \
+			(bool)(sreg & 0xb0); \
+		})
+
+	#endif /* __IAR_SYSTEMS_ICC_ */
+
 #elif CPU_PPC
 	#define NOP                 asm volatile ("nop" ::)
+
 	#define IRQ_DISABLE         FIXME
 	#define IRQ_ENABLE          FIXME
 	#define IRQ_SAVE_DISABLE(x) FIXME
@@ -225,7 +307,7 @@
 	#define CPU_BYTE_ORDER          CPU_LITTLE_ENDIAN
 	#define CPU_HARVARD             1
 
-	/*!
+	/**
 	 * Initialization value for registers in stack frame.
 	 * The register index is not directly corrispondent to CPU
 	 * register numbers. Index 0 is the SREG register: the initial
@@ -237,7 +319,7 @@
 	#error No CPU_... defined.
 #endif
 
-/*!
+/**
  * Execute \a CODE atomically with respect to interrupts.
  *
  * \see IRQ_SAVE_DISABLE IRQ_RESTORE
@@ -251,7 +333,7 @@
 	} while (0)
 
 
-//! Default for macro not defined in the right arch section
+/// Default for macro not defined in the right arch section
 #ifndef CPU_REG_INIT_VALUE
 	#define CPU_REG_INIT_VALUE(reg)     0
 #endif
@@ -327,11 +409,11 @@
 
 #else
 	#define CPU_PUSH_CALL_CONTEXT(sp, func) \
-		CPU_PUSH_WORD((sp), (func))
+		CPU_PUSH_WORD((sp), (cpustack_t)(func))
 #endif
 
 
-/*!
+/**
  * \name Default type sizes.
  *
  * These defaults are reasonable for most 16/32bit machines.
@@ -380,6 +462,7 @@
 #else /* CPU_REG_BITS > 32 */
 	#define SIZEOF_PTR   8
 #endif
+#endif
 
 #ifndef CPU_BITS_PER_CHAR
 #define CPU_BITS_PER_CHAR   (SIZEOF_CHAR * 8)
@@ -424,7 +507,7 @@ STATIC_ASSERT(sizeof(int64_t) * CPU_BITS_PER_CHAR == 64);
 STATIC_ASSERT(sizeof(uint64_t) * CPU_BITS_PER_CHAR == 64);
 #endif
 
-/*!
+/**
  * \def CPU_IDLE
  *
  * \brief Invoked by the scheduler to stop the CPU when idle.
@@ -437,15 +520,12 @@ STATIC_ASSERT(sizeof(uint64_t) * CPU_BITS_PER_CHAR == 64);
 	#if defined(ARCH_EMUL) && (ARCH & ARCH_EMUL)
 		/* This emulator hook should yield the CPU to the host.  */
 		EXTERN_C_BEGIN
-		void SchedulerIdle(void);
+		void emul_idle(void);
 		EXTERN_C_END
-		#define CPU_IDLE SchedulerIdle()
+		#define CPU_IDLE emul_idle()
 	#else /* !ARCH_EMUL */
 		#define CPU_IDLE do { /* nothing */ } while (0)
 	#endif /* !ARCH_EMUL */
 #endif /* !CPU_IDLE */
 
-/* OBSOLETE */
-#define SCHEDULER_IDLE CPU_IDLE
-
 #endif /* DEVLIB_CPU_H */